Transcript Slide 1
SiNANO Workshop Carrier mobility enhancement in strained silicon germanium channels David Leadley University of Warwick Collaborators Warwick Tim Grasby, Andy Dobbie, Chris Beer, Jon Parsons, Evan Parker, Terry Whall IMEC Gareth Nicholas, Marc Meuris, M Heyns, P Zimmerman, Matty Caymax, ++ SINANO partners KTH, Udine, Chalmers, AMO Why is mobility still critical ? e * m High mobility - light mass and minimal scattering ITRS – long term years By 2020, Lg=5nm, Vdd=0.7V Mobility enhancement factor of 1.04 each node Ballistic enhancement factor x2 Double gate structures – light doping Why add Ge? ADVANTAGES – Smaller bandgap – Lighter hole mass – Strain – splits bands and reduces scattering BUT… – Native oxide no good – Band-to-band tunnelling Pseudomorphic Si0.64Ge0.36 on Si 2 Effective Hole Mobility (cm /Vs) 200 150 Mobility doubled SiGe 100 Si Control 50 10m x 160m 0 0.10 0.15 0.20 0.25 0.30 Effective Field (MV/cm) 0.35 0.40 Impact Ionisation 101 I body 100 Si Control I source M-1 (no units) 10-1 SiGe 10-2 10-3 10-4 Vgs = -1.5 V 10-5 0.0 -2.0 -4.0 -6.0 -8.0 Vint (V) Reduced impact ionisation for SiGe, despite higher mobility Nicholas et al, Electronics Letters 41, 20052074 High-k gated SiGe Deposited HfO2 Si cap – oxidises to thin SiO2 interlayer Metal HfO2 SiO2 SiGe Si < 1nm Lowest EOT 12Å Metal gate/HfO2 gate stack development for Si(cap)/Si0.8Ge0.2 channel 1e+0 1013 1e-1 as-deposited 425C, 30min, N2/H2 1e-2 1e-3 -1 Average Dit (cm eV ) 800C, 30sec, Ar 950C, 30sec, Ar 1e-4 -2 Jg (A/cm2) 1012 1e-5 1e-6 1e-7 1e-8 1011 1e-9 as-deposited 425C, 30min, N2/H2 950C, 30sec, Ar 1010 Si Control SiGe 1nm Cap SiGe 2nm Cap SiGe 3nm Cap 950C, 30sec, Ar 1e-10 Thick TiN Thin TiN W 1e-11 1e-12 -4 -3 -2 -1 0 1 2 3 4 Vg (V) Interface state density (W gate) Gate leakage Warwick, AMO, Chalmers High-k/metal gated Si0.8Ge0.2 surface p-channel devices 0.10 Silicon SiGe 1nm cap SiGe 3nm cap SiGe 4nm cap 120 100 2 Effective Mobility (cm /Vs) 0.08 Drain Current (A/m) 140 Silicon SiGe 1nm cap SiGe 3nm cap SiGe 4nm cap 0.06 0.04 80 60 40 0.02 20 L = 50m, W = 50m Vds = -50mV L = 50m, W = 50m 0 0.00 -3 -2 -1 Gate Overdrive (V) 0 0.1 0.2 0.3 0.4 0.5 Effective Field (MV/cm) ........enhancements beating Intel (IEDM 2004) KTH, Warwick, Chalmers, AMO Effective Mobility Best SiGe (25%) devices show mobility enhancement over silicon control Mobility degradation compared to universal – interface roughness and Coulomb scattering important 160 Si Universal Si Control SiGe 1nm Cap SiGe 2nm Cap SiGe 3nm Cap SiGe 4nm Cap SiGe 5nm Cap 120 2 Effective Mobility (cm /Vs) 140 100 80 60 40 20 0 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1 Effective Field (MV/cm) KTH, Warwick, Chalmers, AMO HOT SiGe Hybrid Orientation Technology – n on (100), p on (110) in Si, Yang et al. IEDM 2003 – in Si, no variation with orientation for long channels, but <110> best for short channels, Saito et al VLSI 2006 – 50% enhanced Idsat for SiGe (110) over Si (100), 3.3x for mobility, Liu et al VLSI 2006 [001] [011] [011] (100) substrate [110] (110) substrate NovelPMOSFETs, p-channel/substrate V =-0.1 V, L=25 µm, W=4.6orientations µm DS <112> <111> <110> <110> <100> 0,5 <112> <100> <110> <100> <112> <110> gm [µS/µm] 0,4 0,3 Si Ge 0.8 0,2 0,1 0.2 (110) t =4.5 nm ox Si (100) t =2.6 nm = 3.2 nm ox 0 0 30 60 90 120 150 180 Rotation [deg] … enhancement beating Liu et al (VLSI Symp 2006) KTH, Warwick, Chalmers, AMO Unstrained Ge pMOS High performance Ge pMOS devices using a Si-compatible process flow Zimmerman et al. IEDM 2006 4nm HfO2 2μm Ge on Si substrate 12Å EOT, TDD 107-108 cm-2 PMOS fabricated with Lg ~125 nm IMEC Unstrained Ge Ge + anneal Si IMEC Nit spread 0.2-8x1012cm-2 - affects Ids, gm and Vt Uniformity restored after anneal IMEC Thinner EOT? Si Mobility increase with thinner HfO2 - less charge trapping Starts to leak when too thin ! Ragnarsson et al. IEEE TED 53, 1657 ( 2006) IMEC Mobility in unstrained Ge μ > 300 cm2/Vs Correction required for Rsd in short channel devices Lg<0.25μm IMEC Investigating trapped charge Dit varies across wafer 1011 - 2x1012cm-2 Vt Dit 1 Peak 1 Coulomb 1 Peak 1 Coulomb 1 SR 1 Phonon number of charges,nit Vt Warwick, IMEC Interface charge density Warwick, IMEC Extract Dit in 3 ways at 300K: i. from Vt – average all energies ii. subthreshold slope – specific energy iii. charge pumping Mobility modelling at 4K 1 1 1 At low T, with confinement only have one HH subband. Peak Coulomb SurfaceRoughness 1 Coulomb ni 1 SR 2 2 K F4 Fit using ni and as parameters ... Warwick, IMEC Modelled 4K mobility As grown Annealed ni agrees with values from Dit Δ decreases after anneal from 0.6nm to 0.5nm, hence μSR increases by 35% μ300K must also depend on surface roughness Warwick, IMEC Strain tuning buffers Strained-Si by local strain now in production Si1-yGey virtual substrates for global strain o y~0.2 for s-Si o y~0.5 for s-Si1-xGex o y~0.8 for s-Ge Need low TDD and zero pile-up Terrace Graded VS – better than industrial quality 20% Ge XTEM TDD ≤ 105cm-2, PUD=0 10x10um2 AFM image indicating RMS roughness 1.5nm Warwick, LETI, Jeulich State-of-the-art sSi electron mobility from TG-VSs y = 15 -27% strain 0.6 – 1.1% State of the art F. Driussi et al., ULIS 2007 Warwick, Udine, KTH sGe global platform - 80% terrace grade TDD=3x105/cm-2, PUD = 0, RMS ≈ 8nm Warwick, FZ-Jeulich, LETI Novel thin VS for sGe Strained Si Strained Ge 300nm Si0.2Ge0.8 Grade Seed layer Si Sub 20x20 um2 AFM image. 1.3nm RMS, fully relaxed 80% platform TDD ≈ 106/cm2 range Warwick Strained Ge pMOS 150nm TiN 4nm ALD HfO2 Positive Vt due to gate workfunction ASM, Warwick, IMEC Record Ge mobility via CMOS process Effective Hole Mobility (cm2/Vs) 700 25 nm strained Ge 600 Peak μ = 650 cm2/Vs 500 15 nm 400 strained Ge 300 1 nm Si Unstrained Ge 200 2 nm Si 100 Si/SiO2 universal 0 0 0.2 0.4 0.6 0.8 1 Effective Field (MV/cm) G. Nicholas et al., IEEE EDL 28, 825 (2007) Warwick, IMEC Further comments on s-Ge Full band Monte Carlo calculations, incl. BTBT, SCE etc. show best prospect for pMOS … … strained-Ge directly on Si ! Krishnamohan et al (Stanford) VLSI (2006) For s-SiGe OI, Idsat enhancement in short channels exceeds μ increase in long channel. Tsutomu Tezuka et al. VLSI (2006) nMOS still a problem for Ge … … but tensile strain Si0.1Ge0.9 on relaxed Ge promising. Summary Addition of Ge improves mobility High-k makes Ge viable Mobility enhancements relevant for nanometre scale devices Terrace grading – new generation of virtual substrates 30% TDD ≈ 4 x 104 cm-2 PUD = 0 Warwick LG 30% ≈105 cm-2 TDD Pile-up ≈1 cm-1 High stability sSi layers Relaxation (%) Linear Grading Terrace Grading Strained Si thickness (nm) J. Parsons et al., ULIS 2007 Warwick, FZ-Jeulich Extended Stacking Faults Defect etch image of 20nm strained silicon layer J. Parsons et al., ULIS 2007 PVTEM image of 180nm strained silicon layer Warwick, FZ-Jeulich Extended Stacking Faults “Perfect” dislocation Stacking fault Trailing (30°) Leading (90°) “partial” dislocation “Partial” dislocation S-Si SiGe Stacking faults – effective misfit dislocation blockers? Defect etch images of 30nm strained silicon layer J. Parsons et al., ULIS 2007 Warwick, FZ-Jeulich 50% terrace graded (for sSi) TDD = 2x105 cm-2 PUD = 0 Warwick ≈ 20% TG - slower growth (+sSi) TDD = 4 x 104/cm2 PUD = 0 Schottky Barrier MOSFET- world best? Vds = -1.4 V 1.0E+3 1.0E+2 Tunnelling f(m*) 1.0E+1 1.0E+0 Id (mA/mm) 1.0E-1 1.0E-2 1.0E-3 1.0E-4 1.0E-5 1.0E-6 Thermionic emmision 1.0E-7 1.0E-8 1.0E-9 1.0E-10 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 Vg (V) Measurement D.J. Pearman et al., IEEE Trans ED (accepted 2006) Modelling UCL, Warwick, Glasgow