Transcript Tunnel FET: Present Status and Future Perspectives - MOS-AK

TFET – a possible replacement for
CMOS in low-power applications
Costin Anghel,
Institut Superieur d'Electronique de Paris
(Paris, FR)
08/04/2011 Paris
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Outline:
• Why do we need another new device?
- Power Consumption Problem
- CMOS vs. TFET
• Tunnel FETs
- Operation Principle
- State-of-the-art
• Conclusion
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Outline:
• Why do we need another new device?
- Power Consumption Problem
- CMOS vs. TFET
• Tunnel FETs
- Operation Principle
- State-of-the-art
• Conclusion
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Power Consumption Problem
1. Leakage power
stars to be
dominant in
advanced
technology nodes.
2. The power per
chip continues to
increase.
E.J. Nowak, JRD IBM 2002
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Drain Current, IDS (A/m m)
Scaling limited by the 60mV/dec
-3
10
Lower
V
VTt
-5
10
-7
• The subthreshold slope is limited
to a minimum of 60mV/dec for
CMOS
10
Higher
IOFF
-9
10
• Scaling involves also the scaling of
the threshold voltage (VT).
-11
10
0.0
0.3
0.6
0.9
Gate Voltage, VGS (V)
C. HU - 2009
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“Lowering Vt by 60mV increases
the leakage current (power) by 10
times.”
C. HU – 2009
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Sources of Static Power - CMOS:
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Prof. A.M. IONESCU (EPFL) @ ESSDERC 2009
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Outline:
• Why do we need another new device?
- Power Consumption Problem
- CMOS vs. TFET
• Tunnel FETs
- Operation Principle
- State-of-the-art
• Conclusion
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TFET vs. CMOS
CMOS
TFET
n-type
n-type
Oxide
Gate
Source
n+
i
Oxide
Drain
Source
n+
p+
Gate
i
Drain
n+
CMOS:
TFET:
Pros.: classical device
Pros.: Extremely Low IOFF
ION within the ITRS targets
Cons.: power issue
SS below 60mV/dec
Cons.: Low ION
R&D needed
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Outline:
• Why do we need another new device?
- Power Consumption Problem
- CMOS vs. TFET
• Tunnel FETs
- Operation Principle
- State-of-the-art
• Conclusion
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TFET – the operation principle
Source
VG=0V
VD=1V
p+
Gate
i
Drain
Cutline
n+
Energy [eV]
EC
EV
Location [mm]
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TFET – the operation principle
VG=0V
VD=1V
TFET
ON state
Energy [eV]
Energy [eV]
TFET
OFF state
Location [mm]
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VG=1V
VD=1V
e-
Location [mm]
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Outline:
• Why do we need another new device?
- Power Consumption Problem
- CMOS vs. TFET
• Tunnel FETs
- Operation Principle
- State-of-the-art
• Conclusion
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TFET: State-of-the-art – CNTs
J. Appenzeller et al., Phys. Rev. Lett. 93, (2004).
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TFET: State-of-the-art – Si
Choi et al. Electr. Dev. Lett. 28, pp. 743 (2007).
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TFET: State-of-the-art – Si
Second spacer used to create the gate- drain underlapping
IOFF (~30fA/μm)
ION (~10-7A/μm)
F. Mayer et al, IEDM 2008.
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TFET: State-of-the-art – DG or GAA
DG TFET with strained
Ge heterostructure
channel:
ION high but IOFF and VD high
T. Krishnamohan et al, IEDM 2008.
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TFET: State-of-the-art – DG or GAA
IOFF (~7pA/μm)
ION (~53mA/μm)
ION/ IOFF=107
DIBL = 17mV/V
Chen et al., IEEE EDL, VOL. 30, p. 754, 2009.
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TFET: State-of-the-art – source delta doping
R. Jhaveri, et. al. TED 01/2011, pp. 80.
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K. Jeon, et. al. VLSI, 2010.
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TFET: State-of-the-art – DG or GAA
Source heterojunction
increases the ION
current
IOFF current is
mantained low.
Anne S. Verhulst et al., IEEE EDL, Vol. 29, pp. 1398, 2008.
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TFET: State-of-the-art – DG or GAA
Strained Si at the
Source side –
increase of ION current
IOFF current is
mantained low.
Kathy Boucart et al., IEEE EDL, Vol. 30, p. 656, 2009
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TFET: State-of-the-art – DG or GAA
High k gate dielectrics
- ION current in ITRS
targets
- IOFF current is
mantained low.
Difficult to integrate
high k of 100 or 200
on Si platform…
Schlosser et al. IEEE TED, vol. 56, p. 100, 2009.
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TFET: State-of-the-art – Spacer Influence
High-k spacer
The low-k spacer does not deplete
the source 
Tunneling at the surface of the
device @ highest field 
Increased ION current
Low-k spacer
Anghel et al. APL, vol. 96, p.122104, 2010.
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TFET: Source Position and Film Thickness
4.50
tSi=10nm
0.15
Underlap
4.00
Overlap
Low-k Spacer Low-k Gate
0.13
0.11
3.00
0.09
2.50
2.00
Low-k Spacer High-k Gate
0.07
1.50
ION (nA/mm)
ION (mA/mm)
3.50
0.05
1.00
0.00
94
96
98
100
Hetero-dielectric structures: important ION
variation as a function of source position
0.03
High-k Spacer High-k Gate
0.50
Homo-dielectric structures: low ION
variation as a function of source position
102
104
0.01
106
Source Positon - x S (nm)
Hetero-dielectric structures: important ION
variation as a function of tSi
Anghel et al. accepted for publication IEEE TED, 2011.
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Conclusion:
- TFET presents LOW IOFF and LOW ION and SS
below 60mV/dec.
- TFET can replace in the future the CMOS for
low power applications
Open Question:
- ITRS LSTP roadmap was built on CMOS,
should we rethink this roadmap from another
perspective (i.e. the TFET one)?
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Many Thanks to:
- Hraziia, Anju Gupta, Prathyusha Chilagani
- Prof. Andrei Vladimirescu, Prof. Amara Amara
Thank you for your attention!
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