Transcript PX7510 Training

2015年7月16日星期四
Primarion Confidential
PX7510 Training
Primarion Confidential
2015年7月
16日星期四
Features (1)
• 150 KHz to 2.1 MHz Switching
• Resistor-based address, voltage, frequency and current limit set
• DCR current sense (0 to 3.6V)
– Digital temperature compensation
• Digital control loop
– Voltage control loop with feedforward gain compensation
– 4X Oversampling
• Adjustable droop control
• Current sharing
• Soft-start into prebiased load
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2015年7月
16日星期四
Features (2)
• Soft-start step size1.56mV/step
• Sync up to four controllers in multiphase operation
– Use internal or external frequency reference
• PMBus serial interface
– V, I, T, faults report
– Voltage set and adjustment
– Tracking, sequencing and margining
– Override hardwired settings
• Protection Features
– Output OV/UV, Input UV & OV
– OCP, Thermal shutdown
• Single 5V supply
• 32-pin QFN Package
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•
•
4
–
–
–
–
–
Differential Vsense (2)
Differential Isense (2)
Single ended Temp Sense (1)
V12sen (1)
SMbus
Vbg_ext
• 2-pin bus (2)
Fset
• Tri-state address (1)
Vset
– OutEn (1)
– Fset (1) (also Sync_phase) VSENP
– Vset (1) (also Vscale)
VSENN
– Reset_n (1)
– Imaxset (1)
V12sen
– Vtrim (1)
I Senp
– Vbg_ext (1)
I Senn
– Sync_in (1)
– Smb_alert_n (1)
Temp
Sense
– Ish_gnd (1)
Outputs
– PWM (1)
SClk
SData
– PwrGd (1)
Saddr
– Fault1 (1)
– Fault2 (1)
– Sync_out (1)
Vtrim
Bidirectional
Imaxset
– Iout / Ishare (1)
OUTEN
Power
– 5V (1)
– 3.3V (1) – bypass cap only
– 2.5V (1) – bypass cap only
– GND (paddle)
Sync_out
•
2015年7月
16日星期四
Inputs
Sync_in
•
PX7510 Block Diagram
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5V
3.3 V
2.5 V
Reference
and
Oscillator
GND
ISH_GND
Reset_n
Voltage
Sense
Current
Sense
ADC
Mux
PWM
PID/PWM Control
Temp
Sense
DAC
NVM
SMBus
Iout/Ishare
Smb_alert
Fault Handler
Fault1
Fault2
State Machine
PWRGD
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SDATA
TEMPSEN
25
TEMPSEN
26 25VD50
VD50
PWM
26
27
PWM
NC
27
28
NC
FAULT2
29
FAULT1
28
30
29
FAULT2
SMB_ALERT_N
31
30
FAULT1
SCLK
32
23
3
VD33
24
2
NC
23
22
VD33
NC
PWRGD PWRGD
4
4
21
21
NC
5
20
ISENP
20
ISENP
6
OUTEN
6
19
ISH_GND
19
ISH_GND
IMAXSET IMAXSET
7
7
18
18
VSENN
VSENN
VTRIM
8
8
17
17
VSENP
VSENP
V12SEN
16
V12SEN
15
IOUT
14
15
IOUT
VBG_EXT
14
13
FSET
VBG_EXT
12
VSET
FSET
RESET_N
11
13
10
12
SYNC_OUT
RESET_N
10
9
SYNC_IN 11
VSET
SYNC_IN
9
VTRIM
PX7510
PX7510
SYNC_OUT
OUTEN
16
3
5
22
NC
SADDR
NC
5
24
1
2
SDATA
SADDR
31
32
SCLK
• 32-pin QFN
• 5mm x 5mm
• Pin compatible with future 2VD25
1
phase version
VD25
SMB_ALERT_N
Pinout
NC
ISENN
ISENN
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2015年7月
16日星期四
Freq Sync & Phase Spread
R1
1020
R2

PHASE_SYNC = 270
R3

IOUT
SYNC_OUT
SYNC_IN
PX7510
IOUT
SYNC_OUT
SYNC_IN
PX7510
IOUT
SYNC_OUT
SYNC_IN
FSET
PX7510
IOUT
SYNC_OUT
SYNC_IN
FSET
PX7510
PHASE_SYNC = 180
FSET
PHASE_SYNC = 90
FSET
PHASE_SYNC = 0
C
0.1uF
• Digital control loop to provides phase synchronization capability
• Power Islands can have independent output voltages but optimal phase
spacing and synchronization
• Minimize input ripple and input cap
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PMBus Control Capability
• Turn-on/off & Sequencing
– Programmable turn on/off delay
– Vin on and Vin off settings
• Tracking
– Programmable soft-start ramp rate
• Margining
• Output Voltage
– Fine trim (1.6mV LSB)
– Coarse set (12.5mV LSB, 8-bits)
– Vout Max
– Vout Droop (loadline), 10-bits
– Sense scale factor (Vout/Vsense)
• Override Hardwired Settings
• Manage NVM
– Download parameters from NVM
– Upload parameters to NVM
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2015年7月
16日星期四
• Max duty cycle
• Switching frequency
• Fault Levels
– OOVP, OUVP (fixed)
– OCP
– Overtemp
– IOVP, IUVP
• Fault Response
– Programmable: Continue, Hiccup
or Latched Shutdown (maskable)
– SMBAlert (maskable)
• Clear Faults
• Control Pin Override
• MFR extended commands
– Loop compensation
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PMBus Reporting Capability
• Fault Status
– Output voltage
• UV & OV
– Output current
• Overcurrent
– Input voltage
• UV & OV
– Temperature
• Fault & Warning levels
– Communication
• Protocol violations
• Parameter range check
– MFR defined
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• Telemetry (Reads)
–
–
–
–
–
–
–
–
–
Vin
Vout
Iout
Temperature
Duty Cycle
Frequency
PMBus Rev
MFR ID, Model, Rev, Location
MFR Date & Serial # (ASCII or
binary supported)
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PIN Set Detail
•
•
•
•
•
•
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Six Pin Sets for wide range of POL personalization
FSET - Sets switching frequency and sync functionality
– 100kHz to 1.7MHz range
– Select master/slave for freq sync, phase 0, 90, 180, 270
VSET- Sets output voltage
– 0.4V to 3.6V range, resolution based on scale factor, typical 50mV
– Internal resolution is 12.5mV
VTRIM - Trims Output Voltage
– 6.25mV resolution, +- 50mV range
– Internal resolution is 1.56mV, +-50mV range
IMAXSET - Sets current limit, instantaneous OCP, and filtered OCP per
phase
– 60A range, 4A resolution
– Internal range is 127Amps, 0.5A resolution
SADDR - Sets I2C address
– 16 unique addresses supported
2015年7月
16日星期四
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Current Sense
Rb
Cb
Rsense
This value should be 15mV~35mV
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Vin Sense
Vin
R1 is 63.4K,1%
R1
R2 is 10K,1%
R1 is 1000pF
V12sense
C1
11
R2
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2015年7月
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Temperature sense
Temperature sense
2.87k Ohm 1%
1N4148ws
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Voltage Sense
VSENN
PX7510
VSENP
Divider Resister
Divider resister → R58 : R49 = 1 : ∞
Voltage rang is 0.45~1.8V
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Divider resister → R58 : R49 = 1 : 1
Voltage rang is 0.9~3.6V
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Trim Procedure (Trim Vref)
1. Setting as below in the test page
2. Measure Voltage between “Fault1” to “GND”, this is
“GND” voltage
3. Setting as below in the test page
4. Measure Voltage between “Fault1” to “GND”, this is
DAC voltage.
5. Trim the “VrefCal” until DAC-GND is 1.8724V
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Trim Procedure (Trim Vref TC)
1. Read register address 0x119
2. Calculate Round(0.127 * reg 119(D7:D0) + 20)/4.883) and put it back to register address
0x119(D15:D8)
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Trim Procedure (Trim XV current)
1.
2.
3.
4.
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Write 0x0083 to Register address 0x106.
Write 0xa600 to Register address 0x126.
Measure current from SADDR to GND
Trim XV current (register 0x126 [bit6:bit0]) to 150uA
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2015年7月
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Trim Procedure (Trim Clk_lo)
1. Setting as below in the test page
2. Measure the frequency at the Fault1.
3. Trim the “Lo trim” until Frequency is 39.775MHz
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2015年7月
16日星期四
Trim procedure (Trim Vout)
1. Power on the EV board
2. Measure output voltage
3. Trim Vout-cal until output voltage is equal output
setting.
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2015年7月
16日星期四
Trim Procedure (Trim Internal Temperature Reading)
1. Read Internal TEMP
2. Trim “int_temp_correct” until internal reading is
25degC.
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OCP
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Output Voltage protection
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Input Voltage protection
22
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OTP
23
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Current Sharing
Master
24
Slave
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Current Sharing
25
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Resister Setting - SADDR
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Resister Setting - Frequency
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Resister Setting - Imax
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Resister Setting - Vset
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Resister Setting - Vtrim
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Timing Sequence - Turn On
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Timing Sequence - Turn Off
32