Final Year Project Development of method for improving the light-load efficiency of VRM’s Project Supervisor : Dr. Maeve Duffy March 2009

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VRM

   Voltage Regulator Module Switching Mode Power Supply for Microprocessor The most suitable topography for a VRM is a Multiphase Synchronous Buck Converter 2

Microprocessor Light Load

  Power States Optimize the runtime power consumption Sleep States Idle Power Managements 3

Trends in VRM Design is Microprocessor Loads

 Moore’s Law will apply into the future - Intel   Lower core voltages and higher currents Analysis of recent VRM guideline from Intel

VRM 9.1 VRM 10.0 VRM 11.0 Design Guideline Release Date Icc Icc(max) Icc(step) dIcc/dt VID

2002 75A 81A 54A 450A/uS 1.1-1.85V 2005 85A 100A 70A 560A/uS 0.8375 - 1.6V 2008 130A 150A 100A 1200A/uS 0.5 - 1.6V 4

Synchronous Buck Converter Efficiency

1 L1 2 Cout RLoad Sources of Losses in the power stage  Upper and Lower MOSFET s   Output Inductor Output Capacitor 5

    

Analysis of MOSFET Losses

Conduction for Losses for Upper and Lower MOSFET s Switching Losses for Upper MOSFET Lower MOSFET Body Diode conduction losses Reverse Recovery Losses Gate Driver Losses 6

Capacitor and Inductor Losses

Inductor Losses  DCR and ACR  Hysteresis Losses  Eddy Current Losses Capacitor Losses  ESR (Equivalent Series Resistance) 7

SPICE Modelling of Power Losses

Objective is to use SPICE to measure MOSFET switching losses from the instantaneous products of current and voltage

P avg

 1

T

0 

T v

(

t

) 

i

(

t

)

dt

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Shoot Through during Upper MOSFET Switch On

5 0 A 4 0 A

Drain Source Current

3 0 A 2 0 A

Upper ON

1 0 A 0 A - 1 0 A - 2 0 A 4 9 3 . 0 u s 4 9 3 . 1 u s I ( U 1 1 : D ) I ( U 1 3 : D ) 4 9 3 . 2 u s 4 9 3 . 3 u s 4 9 3 . 4 u s 4 9 3 . 5 u s

Upper OFF

4 9 3 . 6 u s 4 9 3 . 7 u s 4 9 3 . 8 u s 4 9 3 . 9 u s 4 9 4 . 0 u s 5 0 A 4 0 A 3 0 A 2 0 A 1 0 A 0 A

Upper ON

- 1 0 A - 2 0 A 4 9 3 . 0 u s 4 9 3 . 1 u s I ( U 1 1 : D ) I ( U 1 3 : D ) 4 9 3 . 2 u s 4 9 3 . 3 u s 4 9 3 . 4 u s

Upper OFF

4 9 3 . 5 u s 4 9 3 . 6 u s 4 9 3 . 7 u s 4 9 3 . 8 u s 9 4 9 3 . 9 u s 4 9 4 . 0 u s

Eliminating Shoot Through

   Introduction of dead eliminated shoot though on lower MOSFET switch on but not on upper MOSFET switch on A possible cause of shoot through on upper MOSFET switch on is Dv/dt induced turn on of lower MOSFET.

Alan Elbanhawy - Fairchild Semiconductor 10

Dv/dt Induced Turn On of Lower MOSFET

i

(

t

) 

C dv

(

t

)

dt

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MathCAD Efficiency Calculator

 MathCAD displays equation and expression in graphically form, and is aware of SI units.

Easier to track calculations in MathCAD  Used a MathCAD worksheet to calculate the efficiency of a single phase of a synchronous buck converter  The original MathCAD worksheet was a supplement to a paper called “What MOSFET Can Do to Boost the Performance of VRM Design”  Alan Miftakhusdinov - Texas Instruments 12

Generating Rds(0n) from SPICE MOSFET Model

Rds Upper and Lower Mosfet 40 30 Rds 1 Rds 2 20 10 0 2 4 Upper MOSFET Lower MOSFET 6 8 Vgs x Gate s ource Voltage 10 12 Rds (0N) for upper and lower MOSFET s 13

Distributed Inductors

   Paralleling the output inductor Investigating if losses are reduced if inductor are switched out during periods of light loads The effective inductance of the output inductor changes when inductors are switched out.

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Effects of changing inductance of

  Output Ripple Current Output Capacitor ESR Losses I L Reducing L I o Increasing L 15

Conclusion Switching Inductors

6.00

5.00

4.00

3.00

2.00

1.00

1 Inductor 2 Inductors 0.00

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Current per phase Amps

Using Distributed Inductor and switching out inductor during periods of light load does improve VRM efficiency 16

Questions

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