Transcript Ramon Chips RadSafe and J2K

Ramon Chips
Ramon Chips is named in
memory of Col. Ilan Ramon,
Israeli astronaut who died
on board the Columbia
space shuttle, 1/2/2003
Development process of RHBD cell
libraries for advanced SOCs
Tuvia Liran [[email protected] ]
Ran Ginosar [[email protected] ]
Dov Alon [[email protected] ]
Ramon-Chips Ltd., Israel
Ramon Chips
About Ramon Chips
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Private company
Based in Haifa; Israel
Incorporated in 2004
Developed the RadSafeTM technology
Accomplished and delivered several space grade
components to customers
• Focused on advanced IC design for space
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Latest SOC products
JPIC JPEG2000 encoder
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GR712RC Dual core LEON3FT processor
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Outline
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Concepts of RadSafeTM technology
RadSafeTM libraries
Design considerations
Development vehicles used
RadSafeTM 0.13µ technology
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RadSafeTM concepts
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Radiation Hardening is achieved only by design
Same technology for all space applications
Based on standard CMOS technology
Radiation hardening guaranteed by similarity to
previously qualified products/test chips
• All IPs fully developed and owned by Ramon Chips
• Proven immunity on Tower Semi 0.18µ technology
• Complementary methodologies:
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Design For Reliability
Flow for SEU/SET mitigation
Design for testability
Electrical screening
Class S screening flow
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Radiation & Reliability effects
mitigated by RadSafeTM
• Radiation effects:
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TID
SEL
SEU/SET in flip-flops
SEU in SRAMs
SEFI caused by PLL/DLLs
• Reliability effects:
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Electro-migration
Thermal cycling
Chemical effects
Mechanical (shock & vibration)
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Mitigating TID effects
• Advanced CMOS process – ≤0.18µ with STI
• Fixed geometry of transistors – fixed geometry
of parasitic devices; insensitive to placement
• ~30% area penalty – much less than ELT
• TID immunity - >300Krad(Si)
OUT
INA
INB
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Performance under TID stress
0.14
0.12
0.1
Vgs=1.2 before irrad.
Vgs=1.6 before irrad.
Vgs=2 before irrad.
Vgs=0 TID=5
Vgs=0.4 TID=5
0.1000000
Vgs=0.8
TID=5
Vgs=1.2 TID=5
Vgs=1.6 TID=5
Vgs=2 TID=5
Vgs=0 TID=10
Vgs=0.4 TID=10
Vgs=0.8 TID=10
Vgs=1.2 TID=10
Vgs=1.6 TID=10
Vgs=2 TID=10
0.06
Vgs=0.8 TID=15
Vgs=1.2 TID=15
Vgs=1.6 TID=15
Vgs=2 TID=15
Vgs=0 TID=20
Vgs=0.4 TID=20
Vgs=0.8 TID=20
Vgs=1.2 TID=20
Vgs=1.6 TID=20
Vgs=2 TID=20
Vgs=0 TID=50
Vgs=0.4 TID=50
Vgs=0.8 TID=50
Vgs=1.2 TID=50
Vgs=1.6 TID=50
Vgs=2 TID=50
Vgs=0 TID=100
Vgs=0.4 TID=100
Vgs=0.8 TID=100
Vgs=1.2 TID=100
Vgs=1.6 TID=100
Vgs=2 TID=100
Vgs=0 TID=175
Vgs=0.4 TID=175
Vgs=0.8 TID=175
Vgs=1.2 TID=175
Vgs=1.6 TID=175
Vgs=2 TID=175
Vgs=0 TID=250
Vgs=0.4 TID=250
Vgs=0.8 TID=250
Vgs=1.2 TID=250
Vgs=1.6 TID=250
Vgs=2 TID=250
Vgs=0 TID=ann
Vgs=0.4 TID=ann
0.0001000
0.04
0.02
0.0000100
0
Vgs=0.8
TID=ann
0.0000010
Vgs=1.6 TID=ann
-0.02
Vgs=0 TID=ageing
0
0.25
0.5
0.75
1
1.25
1.5
1.07
Vds(V)
2
Vgs=1.2 TID=ageing
Vgs=2 TID=ageing
0.08
Id(A)
Id(A)
PMOS
Vgs=-2 before irrad.
Vgs=-1.6 before irrad.
Vgs=-1.2 before irrad.
Vgs=-0.8 before irrad.
Vgs=-0.4 before irrad.
Vgs=0 before irrad.
Vgs=-2 TID=5
Vgs=-1.6 TID=5
0.1000000
Vgs=-1.2 TID=5
0.06
m
0.04
0.02
0
0
-0.3
-0.6
-0.9
-1.2
Vds(V)
-1.5
-1.8
TID=10
TID=15
TID=20
TID=50
TID=100
TID=175
TID=250
TID=ann
TID=ageing
0.8
1
1.4
1.6
1.8
2
Vgs(V)
Vgs=0 TID=5
Vgs=-2 TID=10
Vgs=-1.6 TID=10
Vgs=-1.2 TID=10
Vgs=-0.8 TID=10
Vgs=-0.4 TID=10
Vgs=0 TID=10
Vgs=-2 TID=15
Vgs=-1.6 TID=15
0.0100000
Vgs=-1.2 TID=15
Vgs=-0.8 TID=15
Vgs=-0.4 TID=15
Vgs=0 TID=15
Vgs=-2 TID=20
Vgs=-1.6 TID=20
Vgs=-1.2 TID=20
Vgs=-0.8 TID=20
Vgs=-0.4 TID=20
Vgs=0 TID=20
Vgs=-2 TID=50
Vgs=-1.6 TID=50
Vgs=-1.2 TID=50
0.0010000
Vgs=-0.8 TID=50
Vgs=-0.4 TID=50
Vgs=0 TID=50
Vgs=-2 TID=100
Vgs=-1.6 TID=100
Vgs=-1.2 TID=100
Vgs=-0.8 TID=100
Vgs=-0.4 TID=100
Vgs=0 TID=100
Vgs=-2 TID=175
Vgs=-1.6 TID=175
Vgs=-1.2 TID=175
0.0001000
Vgs=-0.8 TID=175
Vgs=-0.4 TID=175
Vgs=0 TID=175
Vgs=-2 TID=250
Vgs=-1.6 TID=250
Vgs=-1.2 TID=250
Vgs=-0.8 TID=250
Vgs=-0.4 TID=250
Vgs=0 TID=250
Vgs=-2 TID=ann
Vgs=-1.6 TID=ann
Vgs=-1.2 TID=ann
Vgs=-0.8 TID=ann
before irrad.
TID=5
TID=10
TID=15
TID=20
TID=50
TID=100
TID=175
TID=250
TID=ann
TID=ageing
Vgs=0 TID=ann
TID=ageing
-0.25 Vgs=-1.6
-0.5
-0.75
Vgs=-1.2 TID=ageing
Vgs=-0.8 TID=ageing
Vgs=-0.4 TID=ageing
Vgs=0 TID=ageing
-1
-1.25
-1.5
-1.07
-2
Vgs(V)
TID stress up to 250Krad(Si)
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1.2
Vgs=-0.8 TID=5
Vgs=-0.4 TID=5
0.0000100
Vgs=-0.4 TID=ann
Vgs=-2 TID=ageing
0
-0.02
Vgs=2 TID=ann
0.2
0.4
0.6
Vgs=0.4 TID=ageing
Vgs=1.6 TID=ageing
0.1
TID=5
Vgs=1.2 TID=ann
0
Vgs=0.8 TID=ageing
0.12
before irrad.
Vgs=0.4 TID=15
0.0010000
Id(A)
Id(A)
Vgs=0.4 before irrad.
Vgs=0.8 before irrad.
0.0100000
Vgs=0
TID=15
0.08
NMOS
Vgs=0 before irrad.
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TID effect on ring oscillator frequency
TID(krad)
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Before Irrad.
13.4
50
100
150
200
250
300
Ageing
350
Annealing
13.2
freq. (MHz)
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Dev #1
Dev #2
Dev #3
Dev #4
Dev #5
12.8
12.6
12.4
12.2
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-481 stages of inverters with FO = 4
- Maximum variation in frequency is <0.5%
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Mitigating SEU in flip-flops
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Proprietary circuit
Optimized for area and power
LET threshold - ≥ 38MeV/cm2/mg
SET mitigation by glitch filtering of data
SET Filter for clock by several techniques
Restricting the use of async Set/Reset
All flip-flops on chip accessed by SCAN
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Comparing FF alternatives
Area Power
Tvalid
LET
CLK->out
Threshold
Errors/bit/day
[@LEO](*)
MeV*cm2/mg
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1
1
2.94
5E-7
TMR
4.01
2.6
2.5
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DMR
2.48
2.2
2.5
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DMR+
2.34
2.1
2.5
38.2
4E-14
SEP
1.8
1.6
1.2
38.2
4E-12
SER (**)
1.75
1.5
1.2
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Unprotected
• Relative values
• Refers to standard FF, with scan, same output drive
(*) Refers to 37o inclination, quite solar
(**) Designed for 0.13u only
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I/O cell libraries
• Two libraries:
 For 1.8V core voltage
 For 3.3V core voltage
• Special rad-hard ESD cells
• Special cells:
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LVDS (>400MHz)
SSTL, HSTL, AGP
5V tolerance
Cold spare
• Proven on several chips
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Special design rules for I/O cells
• RH mitigation:
 ≥2 guard rings
 All NMOS transistors ringed by P+/GND
 Special ESD considerations
• Other considerations for space ICs:
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Large pitch/size pads – enables thick Al bond wires
Relaxed layout rules – reduced thermo-mechanical stress
Dual slope transition – reduced ringing
Double supply pads – reduced inductance & density
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RadSafe SRAM cell
BL
Many NMOS devices
connected to bit-lines
BLB
WL
BL
BLB
WLB
Conventional SRAM cell
Only PMOS devices
connected to bit-lines
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RadSafeTM SRAM cell
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Examples of SRAM cores
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SRAM cell libraries
• Variable sizes, up to 2Kx40
• Two types of SRAM cores:
 Single / dual port (>250MHz / >120MHz)
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Two operation voltages: 1.8V, 3.3V
DPRAM performs read & write access per cycle
Integrated EDAC & BIST in each core
Very low power; zero standby power
Protected from all radiation effects:
 MBU is eliminated
 LET threshold 3 MeV·cm2/mg (before EDAC correction)
 In tests, all errors corrected by EDAC
• Testability features:
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Complementary BIST logic
Speed control
Weak write
Iddq compatibility
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All-digital DLL cores
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Three DLL cores for 3 frequency ranges
Locking guaranteed & fast
Immediate re-locking
0.05 mm2/core
8 mW/core @0.18u
Highly protected from radiation effects
Can be placed anywhere in the core
Powered by core supply lines
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Technology development chips
RADIC2
•1.8/3.3V transistors
•1.8/3.3V std. cells
•1.8/3.3V ring oscillators
•1.8/3.3V shift registers
•4Kbit SRAM
•ADDLL
•FPGA converted chip
RADIC3
•1.8V transistors
•1.8V std. cells
•1.8V ring oscillators
•1.8V shift registers
•Several FF types
•256Kbit DPRAM
•ADDLL
•LVDS I/O buffers
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GR702RC
•LEON3FT core by GR
•Fully automatic flow
•2 SpW ports w LVDS
•2 ADDLL
•10 SRAM cores
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RadSafe™ 0.13µ technology
• Density:
 Logic - >120Kgates/mm2
 SRAMs - >200Kbit/mm2
(40K at 0.18m)
(80K at 0.18m)
• Power - <40% of 0.18µ
• Speed - >200MHz [for large chips]
• Special IPs:
 10 bit, 1Msps, 1mW SAR ADC
• Status:
 Test chip ready for production
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RADIC4 – Test chip for RadSafe_013
technology
3 shift
registers
3 delay lines/
SET monitor
10b RH ADC
(1Msps,1mW)
4Kx72 RH
SRAM
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NMOS/PMOS
Xtors
4Kx72 RH
SRAM
With process
enhancement
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10b Analog to Digital Converter
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Resolution: 10 bit
Sampling rate: 0.5Msps
Power: <1.5mW
Area: ~0.03mm2
TID: >300Krad (target)
Process: 0.13µ
Voltage: 3.3/1.2V
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Summary
• RadSafe™ by Ramon Chips
Using standard process
Using standard EDA tools & flow
Proven Rad-Hard-by-design on several chips
Optimized for performance, power & reliability
RH considerations applies to all levels of design
flow
 0.13µ process provides significant performance
advantages
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