Transcript Developers Conference

High-Speed
Detection Handshake
Considerations
Jerome Tjia
Philips Semiconductors
May 9, 2001
2
Why This Topic?
Chirping process is the pre-requisite to highspeed operation (failure in chirping process
defaults back to FS/LS mode)
A few “gotchas” in the implementation
If not properly designed, it will become a major
interoperability issue
May 9, 2001
3
Reset/Speed Detection
Protocol
High-speed capable devices are reset by 10ms
of continuous SE0 (same as USB 1.1)
During Reset, a high-speed capable device
“chirps” to the hub
If a USB 2.0 hub detects this chirp, it completes
the handshake by chirping back to the device
within the Reset
If the handshake is completed during Reset,
both hub and device come out of Reset in
high-speed mode
May 9, 2001
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Reset Handshake Signaling
Device chirp is a Chirp K (detected with hub’s
high-speed receiver)
Device chirps by driving current in D- line while
leaving D+ pullup in place and leaving
terminations inactive
Hub chirp is a series of alternating Chirp
J’s and K’s
Hub chirps by driving current into D+ or D- line
Reference state machines included in Appendix C
May 9, 2001
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Timeline for Reset
Start of
Reset
Start of
Hub Chirp
Hub
> 10 ms
End of
Hub Chirp
< 100 μs
End of
Reset
100-500 μs
D+
μSOF
SE0
Device Chirp SE0
Hub Chirp
SE0 HS idle μSOF
Device
D–
3.0-3.125 ms
Start of
Reset
May 9, 2001
100-875 μs
> 1.0 ms
< 7.0 ms
Device
Start of
reverts
Device Chirp
to FS
End of
Device Chirp
< 500 μs
Device
detects
Hub Chirp
Device
reverts
to HS
6
A Closer Look at SE0
Level During Reset
During reset, SE0 level are not exactly at ground
1.5 k ohm pull-up resistor on D+ is not
disconnected yet
Results in a little offset voltage
May 9, 2001
7
USB 2.0 Transceiver
Functionality
+3.3V
Rpu_Enable
HS_Current_Source_Enable
HS_Drive_Enable
HS_Data_Driver_Input
High Speed Current Driver
Legacy Driver
LS/FS_Data_Driver_Input
Assert_Single_Ended_Zero
FS_Edge_Mode_Sel
LS/FS_Driver_Output_Enable
Rs
Rs
Data+
HS_Differential_Receiver_Output
HS Differential Data Receiver
Differential_Receiver_Enabled
Rpu
Data-
Transmission Envelope Detector
Legacy_Differential_Receiver_Output
Legacy Data Receiver
HS_Disconnect_Detected
SE_Data+_Receiver_Output
Disconnection Envelope Detector
Single Ended Receivers
SE_Data-_Receiver_Output
May 9, 2001
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DC Condition During Reset
DC condition during reset
VTERM
(3.3 +/- 0.3 V)
RPU
(1k5 +/- 5%)
D+
DON
Z HSDRV
(45 ohm
+/- 10%)
OFF
R PD
(15k +/- 5%)
Host/Hub
May 9, 2001
Device
9
DC Voltage Levels
During Reset
DC Voltage at D+/D- lines:
– VD- = 0V
– VD+ = VTERM * (ZHSDRV // RPD) / ((ZHSDRV // RPD) + RPU)
VD+ (min, typ, max) voltage = (79, 96, 120) mV
– VTERM = 3.3 +/- 0.3V
– ZHSDRV = 45 ohm +/- 10%
– RPU = 1k5 +/- 5%
– RPD = 15k +/- 5%
This offset voltage is termed “Tiny-J”
May 9, 2001
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Will Tiny-j Become Valid J?
Two conditions to become valid-J:
– Differential receiver able to indicate J data
– Squelch threshold must be crossed to
indicate valid data
Differential receiver is normally very sensitive
– Though spec is 150 mV (differential)
– A tiny-J of 96 mV typical voltage level will most likely
be detected as a ‘J’
Squelch threshold may potentially be crossed too
Very likely that tiny-J be interpreted as a valid J
May 9, 2001
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Overlapping Squelch
Threshold and Tiny-J levels
Tiny-J level
Squelch threshold
150 mV
120 mV
100 mV
79 mV
May 9, 2001
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High-Speed Detection
Handshake
Reset Protocol and High-speed Detection Handshake
D+
3.0 V
900 mV
800 mV
800 mV
D-
96 mV
(120 mV wc)
FS Idle
Squelch:
100-150 mV
differential
0 mV
FS SE0
Chirp K
FS SE0
Alternating Chirp K & J FS SE0
HS Idle
"Tiny J"
May 9, 2001
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Warning #1: Hub/host
Should Ignore Tiny-J
During reset, hub/host is looking for a chirp-K
Potentially, it can receive a valid chirp-J
Hub/host should ignore this chirp-J
– It should not reject or decide that the attached device
is not high-speed capable at this time
It should continue to listen for a chirp-K for 7 ms
or until the end of reset period
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Warning #2: End of
Chirp-K Timing
End of chirp-K is another tiny-J level!
Cannot rely solely on squelch detector
deassertion as the marker for end of chirp-K
Use non zero data pattern to indicate
end of chirp-K
End of chirp-K -> alternating chirps K,J
May 9, 2001
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Warning #3: Transceiver
Design Guideline
Although tiny-J can be handled by upper digital
logic layer of the host/hub, it’s double assurance
to tackle it in the transceiver
To ensure that tiny-J is not interpreted as a valid J
– ensure squelch threshold higher than tiny-J, by:
– Increasing (doubling) squelch threshold during
chirping period (will this violate spec?)
OR
– Designing squelch threshold voltage to be 120-150 mV
(tough?, no noise margin)
May 9, 2001
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Overlapping Squelch
Threshold and Tiny-J levels
Tiny-J level
Squelch threshold
150 mV
120 mV
100 mV
79 mV
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17
Other/minor
Warnings - Device
Device starts driving chirp-K upon detection
of reset signaling
Device Reset can happen from different states
– Reset from (FS) suspended state
– Reset from FS non-suspended state
– Reset from HS non-suspended state
Reset from HS non-suspended state
– initially indistinguishable from suspend
– wait for 3 ms, switch to FS, wait TWTRSTHS (~ 500 us)
debounce and settling time and then detects SE0
May 9, 2001
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Timeline for Reset
Start of
Reset
Start of
Hub Chirp
Hub
> 10 ms
End of
Hub Chirp
< 100 μs
End of
Reset
100-500 μs
D+
μSOF
SE0
Device Chirp SE0
Hub Chirp
SE0 HS idle μSOF
Device
D–
3.0-3.125 ms
Start of
Reset
May 9, 2001
100-875 μs
> 1.0 ms
< 7.0 ms
Device
Start of
reverts
Device Chirp
to FS
End of
Device Chirp
< 500 μs
Device
detects
Hub Chirp
Device
reverts
to HS
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Summary
Specification is OK as is
Tiny-J needs to be taken care of properly
Watch out for warnings/gotchas in transceiver,
host/hub and device design
Will become a major interoperability issue if not
properly designed
May 9, 2001
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