Transcript Example page 139 - Faruk Hadziomerovic

Review
1.
Data types and operations:
•
•
•
•
2.
3.
4.
Numbering systems: unary, binary, octal, decimal hexadecimal
Binary addition and substraction using 2’s complement arithmetic
Logical operation: AND, NOT, OR.
Floating point format and ASCII format for input/output
Digital Logic:
•
Boolean algebra and implementation with Combinational Circuits
•
Implementation of Boolean functions with PLAs
•
Feedback and RS flip-flop. Gated D flip-flop
•
Register as array of D flip-flops
•
Memory as array of registers: address space and addressability
•
Sequential Circuits (FSM): state diagrams, block diagram, race condition and
master-slave flip-flop.
•
FSM implementation with micromemory.
•
•
•
•
•
•
•
•
•
Von Neumann Concept:
CPU, Memory, I/O
CPU: ALU, Control Unit
Instructions (ISA): format, addressing modes
Instruction executions: fetch cycle, execution cycle
Computer Architecture (Data Path) around single bus, signals
Micro-architecture and FSM of the LC-3 computer
Programming
11/22/2005
Machine language programming: LC-3 editor, LC-3 simulator
Problem solving and structured programming
Common bugs and debugging
SSST: CS130 F. Hadziomerovic
1
Data types and operations:
Numbering systems: unary, binary, octal, decimal, hexadecimal
Floating point format and ASCII format for input/output
ASS#1
Question 2 (IEEE floating point standard): transform the speed of light c = 300,000,000 m/sec
into the floating point number. Show your steps. (You may use approximation when converting from base 10 to base 2)
(25 points)
300,000,000 = 1.117587*228 = (1 + 0.00011110000110100011000)*2155-127 =
0 100 1101 1000 1111 0000 1101 0001 1000 =x 4D8F0D18
Midterm
Question 1:Write in binary the maximum positive number in floating point binary format. (5 points)
0 11111110 11111111111111111111111 = x7F7FFFFF
What is the value of this number (to express it you can use powers of 2)? (5 points)
2127 (1 + 1 – 2-23) ~ 2128
If the same number would be interpreted as 2 complement binary format what will be the value? (5 points).
231 – 1 – 223 ~ 231
Write 0 (zero) in floating point format and express it in hexadecimal. (5 points)
0 00000000 00000000000000000000000 = x00000000
Question 1: In a numbering system with base N what are the values of single digit? (5 points)
0 1 2 3 4 … N-1
Which numbering system base was the closest to Roman way of writing numerals? (5 points)
1
How many different numbers can be represented in floating point format? (5 points)
232
In floating point format the numbers are not evenly distributed on the numbering line. What is
the biggest and the smallest difference between two consecutive numbers? (5 points)
Biggest = 2104 smallest = 2-149
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Digital Logic:
Boolean algebra and implementation with Combinational Circuits
Implementation of Boolean functions with PLAs
Ass #1:
Question 3 (combinational circuit): Given the following truth table, generate the gate-level logic circuit,
using the implementation algorithm referred to in Section 3.3.4.
(25 points)
ABC
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
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Z
1
0
0
1
0
1
1
0
C
B
A
Z
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3
Digital Logic (cont.):
Implementation of Boolean functions with PLAs
Any logical functions (here X and Y) can be implemented by two levels circuits: ANDs and ORs.
A
B
C
X
Y
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Digital Logic (cont):
Feedback and RS flip-flop.
b
a
b
CC
a
p
c
a
b
p
0
0
1
1
0
1
0
1
stable
0
1
x
1
x
1
b: 0
1
0
1
b: 1
0
0
0
a: 0
1
a: 1
0
b
a
x
1
x
1
0
0
b
b’
c
c
1
0
p = a + b’c
p
a
b
p
time
a
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c
p
a
p
x
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p’
5
Digital Logic (cont):
Gated D flip-flop
Register as array of D flip-flops
One bit register = memory cell
WE = Clock pulse
in bit
gate
RS
out bit
Eight bit register
b7
b6
b5
b4
b3
b2
b1
b0
WE
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Digital Logic (cont):
Register as array of D flip-flops
Ass#2
Question 2 Incrementer: PC increments by 1 every fetch cycle. Draw block diagram (5 points), truth table (5 points),
and detailed implementation (10 points) of one bit cell with a single line signal: 1 – increment, 0 – do not increment.
Incr. truth table
Di Ci Do Co
PC
clock
incrementer
0
c = incr
0
0
1
1
0
1
0
1
0
1
1
1
0
0
0
1
cl
Do
1
co
0
1
ci
Di
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Digital Logic (cont):
Memory as array of registers: address space and addressability
WE
N address
lines (bus)
address
space = 2N
a
d
d
r
e
s
s
d
e
c
o
d
e
r
memory 0
memory 1
memory 2
memory 3
memory 4
memory 5
memory 6
memory 7
M data lines (bus)
adressability = M
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Digital Logic (cont):
Memory details
address
word select
word WE
input bits
write
enable
output bits
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Digital Logic (cont):
Memory as array of registers: address space and addressability
Midterm
Question 3: Suppose you have three memory blocks 1 kB each. Consequently each block has 10 address bits (wires),
8 data bits (wires), 1 r/w bit (wire), and 1 enable bit (wire). If enable bit = 1 memory output wires (data) are active,
else they are high impedance. Connect these blocks to the MAR and MDR to have 3 kB memory capacity. (15 points)
A11
A10
11
A0-A9
and r/w
E
1 KB
E
1 KB
E
1 KB
Data
8
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Digital Logic (cont):
Sequential Circuits (FSM): state diagrams, block diagram, race condition and
master-slave flip-flop.
Ass#1:
Question 4 (sequential circuit): given the state diagram below implement sequential circuit
with D flip-flops: draw block diagram, state table, and implement combinational circuit. (25 points)
0
0
00
01
combinational circuit
B
1
1
I
1
0
C
B+
C+
D
10
D
cl
State
Current next
I B C B+ C+
0 00 0 0
1 00 0 1
0 01 0 0
1 01 1 0
0 10 0 1
1 10 0 0
0 11 x x
1 11 x x
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I
B
C
B+
I
B
C+
I
B
C
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Digital Logic (cont):
FSM implementation with micromemory.
Ass#2
Question 1 Microsequencing: Implement the traffic danger sign from 3.6.4. (FSM is in Fig.1) using micromemory
and microsequencer given below (Fig. 2). How many flip-flops do you need (minimum)? (10 points).Write the
micromemory content (20 points). Draw detailed microsequencer (10 points),
SW
SW
00
0
1
All
Off
0
01
1,2
On
Microsequencer
Next state
0
0,
1
All
On
11
1
1
clock
current state
=address
Micromemory
1,2,3,4
On
microinstruction
10
lamps
Fig. 2.
Fig. 1.
From micro
instruction
a. two flip-flops.
Address next st
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0
1
0
1
1
1
2
0
1
1
1
lamps
3 4
0 0
0 0
1 1
1 1
5
0
0
0
1
1
SW
00
0
Next state
b. micromemory.
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c. microsequencer.
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Digital Logic (cont):
FSM implementation with micromemory.
Midterm
Question 4: Consider the sequential circuit in figure below (textbook Fig 3.43).
Fill in the next state table. (5 points). Draw the state diagram. (5 points).
Implement the same circuit using micromemory and give the micromemory content. (15 points).
Z
X
S0
D0
S1
D1
X=0,
1
X S0 S1 D0 D1 Z
0 0 0 0 0 0
0 0 1 1 1 1
0 1 0 0 0 1
0 1 1 0 1 1
1 0 0 0 0 0
1 0 1 1 1 1
1 1 0 0 1 1
1 1 1 0 1 1
00
01
X=1
X=0,1
X=0
10
X=0,1
11
Clock
X
X’ D1+ D +
0
Addr
next
S0 S1 D0+ D1+
0 0
0 0
0 1
1 1
1 0
0 0
1 1
0 1
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Z X’
1
1 1
1
Micro
mem
S0
D0
S1
D1
Clock
Z
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Von Neumann Concept
Instruction executions: fetch cycle, execution cycle
Instructions (ISA): format, addressing modes
MEMORY
ACC - Accumulator Register
ALU - Arithmetic Logic Unit
CPU - Central Processing Unit
E - Execution phase
F - Fetch phase
I/O - Input Output (Terminal)
MAR - Memory Address Register
MDR - Memory Data Register
OP - Instruction operation
PC - Program Counter
M
A
R
I/O
E
F
E
OP
MDR
F
ADDRESS
ALU
GOTO
PC
ACC
CPU
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Von Neumann Concept (cont.):
Instructions (ISA): format, addressing modes
Ass#2
Question 4 Instruction Fields: Assume that memory in Question 3 is 10 bits wide. and instructions use only
direct memory addressing mode (IR address field is the operand address) without bit extensions.
What is the maximum memory capacity? Briefly explain your answer. (15 points).
OP
REG
OPERAND ADDR
2 bits for: LD register, add, sub, ST.
1 bit for register: 0 – A, 1 – B
And remaining 7 bits for operand address. Therefore max memory capacity = 2 7 = 128.
Addressing modes: immediate (operand in instruction), register (reg in instruction, operand in register)
Memory (memory address/offset in instruction, operand in memory): PC-relative, Base+offset, indirect.
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Von Neumann Concept (cont.):
Instructions (ISA): format, addressing modes
15 14 13 12 11 10
9
8
7
6
5
4
3
0
0
2
1
0
ADD
0
0
0
1
DR
SR1
0
ADD
0
0
0
1
DR
SR1
1
AND
0
1
0
1
DR
SR1
0
AND
0
1
0
1
DR
SR1
1
BR
0
0
0
0n
z
JMP
1
1
0
0
0
JSR
0
1
0
0
1
JSRR
0
1
0
0
0
LD
0
0
1
0
DR
PCoffset9
+
LD DR, Label: DR <- mem[PC + SEXT(PCoffset9)]
LDI
1
0
1
0
DR
PCoffset9
+
LDI DR, Label: DR <- mem[mem[PC + SEXT(PCoffset9)]]
LDR
0
1
1
0
DR
+
LDR DR, BaseR, #-5: DR <- mem[BaseR + SEXT(offset6)]
LEA
1
1
1
0
DR
+
LEA DR, Target: DR <- PC + SEXT(PCoffset9)
NOT
1
0
0
1
DR
RET
1
1
0
0
0
0
0
1
1
RTI
1
0
0
0
0
0
0
0
0
ST
0
0
1
1
SR
PCoffset9
ST SR, Label: mem[PC + SEXT(PCoffset9)] <- SR
STI
1
0
1
1
SR
PCoffset9
STI SR, Label: mem[mem[PC + SEXT(PCoffset9)]]<- SR
STR
0
1
1
1
SR
TRAP
1
1
1
1
res.
1
1
0
1
0
p
0
SR2
imm5
0
0
SR2
imm5
+
ADD DR, SR1, SR2: DR <- SR1 AND SR2
+
ADD DR, SR1, imm5: DR <- SR1 AND SEXT(imm5)
+
AND DR, SR1, SR2: DR <- SR1 AND SR2
+
AND DR, SR1, imm5: DR <- SR1 AND SEXT(imm5)
PCoffset9
0 BaseR
0
0
BR Next, BRzp Loop: if (cond) PC <- PC + SEXT(PCoffset9)
0
0
0
0
JMP R2: PC <- R2
PCoffset11
0
0
0 BaseR
0
JSR Label: R7 <- PC , PC <- PC + SEXT(PCoffset11)
0
BaseR
0
0
0
0
offset6
PCoffset9
SR
BaseR
0
0
JSR Label: R7 <- PC, PC <- BaseR
1
1
1
1
1
1+
NOT DR, SR: DR <- NOT(SR)
1
0
0
0
0
0
0
RET ; PC <- R7
0
0
0
0
0
0
0
RTI: PC, PSR <- top two values from the stack
offset6
trapvetor8
STR SR, BaseR, offset6: mem[BaseR + SEXT(offset6)] = SR
TRAP trapvector: R7 <- PC, PC <- mem[ZEXT(trapvector)]
generates illegal code exception
Addressing modes: immediate (operand in instruction), register (reg in instruction, operand in register)
Memory (memory address/offset in instruction, operand in memory): PC-relative, Base+offset, indirect.
11/22/2005
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Computer Architecture:
Computer Architecture (Data Path) around single bus, signals
Ass#2
Question 3 Data Path: assume very simple computer with two registers A and B, that can perform
operations below.
A <- M[IR],
B <- M[IR],
A <- A + B,
A <- A – B,
M[IR] <- A
Draw the necessary data path (around single bus architecture) to carry these operations by showing
registers (including PC,IR, MAR, and MDR), adders, gates, etc. , data paths and control signals (with
arrowheads not filled in). (25 points)
r
Memory
LDMAR
LDMDR
MDR
MAR
w
MDRon
Aon
IRon
PCon
PC
LDIR
bus
IR
LDA
A
LDB
B
invert
inv
ALU
11/22/2005
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+1
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Computer Architecture (cont.):
Computer Architecture (Data Path) around single bus, signals
Micro-architecture and FSM of the LC-3 computer
Midterm
Question 2: LC-3 architecture is built around a single bus (ref. textbook Fig. C.3). How many wires are in the bus?
(5 points)
16
List the registers that the bus transfers data from/to?
(5 points)
PC, IR, R0 to R7, MAR, MDR
If you need to transfer data from source to destination register which signals should you activate (at the same time)?
(5 points)
GateSource and LD.Destination
Midterm
Question 2: LC-3 architecture is built around a single bus (ref. textbook Fig. C.3). How many wires are in the bus?
(5 points)
16
Can you have LC-3 architecture without using MAR and MDR? How many wires will buss have to have?
(5 points)
32
In this architecture, which signals you need to activate to fetch an instruction?
(5 points)
PC.on ,
LD.IR
and r
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Programming
Machine language programming: LC-3 editor, LC-3 simulator
Midterm
Question 5: Consider the program below: Translate the program to binary form (10 points). Interpret instructions
in mnemonic form (10 points). What does the program do? (5 points)
Address
Content
a. Binary
b. Mnemonic
x3000
x54A0
0101 0100 1010 0000
AND R2, R2, #0
x3001
x14AA
0001 0100 1010 1010
ADD R2, R2, #10
x3002
xE2FD
1110 0010 1111 1101
LEA R1, x3100
x3003
xF023
1111 0000 0010 0011
TRAP IN
x3004
x7040
0111 0000 0100 0000
STR R0, R1, #0
x3005
x1261
0001 0010 0110 0001
ADD R1, R1, #1
x3006
x14BF
0001 0100 1011 1111
ADD R2, R2, # -1
x3007
x03FB
0000 0011 1111 1011
BRp x3003
x3008
xF025
1111 0000 0010 0101
TRAP HALT
c. Program stores 10 input characters into 10 memory locations starting with x3100.
Question 5: Consider the program below: Translate the program to binary form (10 points). Interpret instructions
in mnemonic form (10 points). What does the program do? (5 points)
Address
Content
a. Binary
b. Mnemonic
x3000
x5260
0101 0010 0110 0000
AND R1, R1, #0
x3001
x126A
0001 0010 0110 1010
ADD R1, R1, #10
x3002
xE40D
1110 0100 0000 1101
LEA R2, x3010
x3003
x6080
0110 0000 1000 0000
LDR R0, R2, #0
x3004
xF021
1111 0000 0010 0001
TRAP OUT
x3005
x14A1
0001 0100 1010 0001
ADD R2, R2, #1
x3006
x127F
0001 0010 0111 1111
ADD R1, R1, #-1
x3007
x0BFB
0000 1011 1111 1011
BRnp x3003
x3008
xF025
1111 0000 0010 0101
TRAP HALT
c. Prints the ASCII content of 10 consecutive memory locations starting with x3010.
11/22/2005
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Programming (cont.):
Problem solving and structured programming: Example page 139
Common bugs and debugging
Number of occurences (count): R2 <- 0
Input char from keyboard into R0: trap 23
Initialize pointer: R3 <- starting file address
Get char from file: R1 <- M[R3]
yes
R1 ?= EOT
Prepare output:
R0 <- R2 + x30
no
yes
Incr.count
R2<-R2+1
R0 ?= R1
Display char: trap 21
no
halt: trap 25
Incr.point
R3<-R3+1
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Mnemonic
program that displays how many times the keyed character shows in a file
X3000
x3001
x3002
X3003
X3004
X3005
X3006
X3007
X3008
x3009
x300A
x300B
x300C
x300D
x300E
X300F
X3010
AND R2,R2,#0 ; R2 <- 0
Trap x23 ; input char
LD R3, start file
LDR R1,R3,#0 ; get char
ADD R4, R1, #-4 ; ‘eot’ = 4
BRz x300D
NOT R1
ADD R1,R1,#1
ADD R1, R1, R0
BRnp, x300B
ADD R2,R2,#1
ADD R3, R3,#1
BRnzp x3003
LD R0, x3012
ADD R0, R0, R2 ; ASCII count
TRAP x21 ; display R0
TRAP x25 ; halt
x3000
x3001
x3002
x3003
x3004
x3005
x3006
x3007
x3008
x3009
x300A
x300B
x300C
x300D
x300E
x300F
x3010
X3011
X3012
start address of a file
0030 ; ASCII_offset
x3011 0011000000010011
x3012 0000000000110000
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0101010010100000 x54A0
1111000000100011
xF023
0010011000001110
x460E
0110001011000000
x62C0
0001100001111100
x187C
0000010000000111
x0407
1001001001111111
x927F
0001001001100001
x1261
0001001001000000
x1240
0000101000000001
x0A01
0001010010100001 x14A1
0001011011100001 x16E1
0000111111110110 x0FF6
0010000000000100 x2004
0001000000000010 x1002
1111000000100001 xF021
1111000000100101 xF025
SSST: CS130 F. Hadziomerovic
x3013
x0030
21
Assembly language
AGAIN
NEXT
OUTPUT
ASCII
PTR
.ORIG x3000
AND R2, R2, #0
LEA R3, PTR
Trap x23
LDR R1, R3, #0
ADD R4, R1, #-4
BRz OUTPUT
NOT R1, R1
ADD R1, R1, #1
ADD R1, R1, R0
BRnp NEXT
ADD R2, R2, #1
ADD R3, R3, #1
BRnzp AGAIN
LD R0, ASCII
ADD R0, R0, R2
TRAP x21
TRAP x25
.FILL
x0030
.STRINGZ "Hello world"
; R2 is a counter initialize to 0
; PTR is start address of a file
; get input character to R0 input char
; get char from a file
; check the end of file ‘eot’ = 4
; file char vs input char
; char found increment counter
; increment pointer in a file
; ASCII offset
; count in ASCII
; display count (R0)
; halt
; ASCII_offset
; file
.END
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Assembly format
label
opcode operands
AGAIN
LDR
R1, R3, #0
; comment
; get char from a file
Pseudo-ops (Assembler Directives)
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.ORIG x3100
.FILL #10
.BLKW 11
.STRINGZ “Hello”
.END
; (x – hexadecimal, # - decimal) PC = x3100
; this location will be filled with decimal 10
; 11 successive locations are reserved
; 5 successive locations are loaded with char string
; end of assembly program
.EXTERNAL
; cross-reference
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How assembler works
Two passes:
First pass: Make a symbol table
AGAIN
NEXT
OUTPUT
ASCII
PTR
.ORIG x3000
AND R2, R2, #0 ; initialize counter R2 to 0
LEA R3, PTR ; PTR is start address of a file
Trap x23
; get input char to R0
LDR R1, R3, #0 ; get char from a file
ADD R4, R1, #-4 ; check the end of file ‘eot’ = 4
BRz OUTPUT
NOT R1, R1
ADD R1, R1, #1
ADD R1, R1, R0 ; file char vs input char
BRnp NEXT
ADD R2, R2, #1; char found incr counter
ADD R3, R3, #1; increment pointer in a file
BRnzp AGAIN
LD R0, ASCII ; ASCII offset
ADD R0, R0, R2 ; count in ASCII
TRAP x21
; display count (R0)
TRAP x25
; halt
.FILL x0030
; ASCII_offset
.STRINGZ "Hello world"
; file
.END
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Symbol
Address
AGAIN
x3003
NEXT
x300B
OUTPUT
x300D
ASCII
x3011
PTR
x3012
Second pass: Translate mnemonic
using symbol table
x3000 0101 010 010 1 00000
x3001 1110 011 000010000 (x3012 – x3002 = x10)
X3002 1111 0000 00100011
X3003 0110 001 011 000000
X3004 0001 100 001 1 11100
X3005 0000 010 000000111 (x300D – x3006 = x07)
X3006 1001 001 001 111111
X3007 0001 001 001 1 00001
X3008 0001 001 001 0 00 000
Etc.
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.EXTERNAL ; beyond a single assembly program
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
21.
1.
2.
3.
4.
AGAIN
NEXT
OUTPUT
ASCII
PTR
STARTofFILE
.ORIG x3000
AND R2, R2, #0
LD R3, PTR
Trap x23
LDR R1, R3, #0
ADD R4, R1, #-4
BRz OUTPUT
NOT R1, R1
ADD R1, R1, #1
ADD R1, R1, R0
BRnp NEXT
ADD R2, R2, #1
ADD R3, R3, #1
BRnzp AGAIN
LD R0, ASCII
ADD R0, R0, R2
TRAP x21
TRAP x25
.FILL x0030
.EXTERNAL STARTofFILE
.FILL STARTofFILE
.END
; initialize counter R2 to 0
; PTR is start address of a file
; get input char to R0
; get char from a file
; check the end of file ‘eot’ = 4
; file char vs input char
; char found incr counter
; increment pointer in a file
; ASCII offset
; count in ASCII
; display count (R0)
; halt
; ASCII_offset
.ORIG x4000
.STRINGZ "Hello World"
.FILL x04
.END
Assembler does not know STARTofFILE location and .EXTERNAL tells it that this will be linked later.
When linker is called then cross-references (unresolved labels) are filled in from other Symbol Tables.
11/22/2005
SSST: CS130 F. Hadziomerovic
25
Memory mapped Input/Output (I/O)
x0000
15 14
0
xFE00
KBSR
15
87
0
KBDR
memory
xFE02
15 14
0
DSR
xFE04
15
87
DDR
0
xFE06
xFDFF
xFE00
KBSR[15] = 1; new char in KBDR
I/O registers
DSR[15] = 1 ; DDR is ready for new char.
xFFFF
11/22/2005
SSST: CS130 F. Hadziomerovic
26
Memory mapped Input/Output (I/O) architecture
bus
GateMDR
MAR
LD.MAR
R.W
MDR
LD.MDR
Memory
E
MIO.EN
KBSR
Address
Control
DSR
set
re set
KBDR
DDR
2
test
keyboard
15 14
0
15 14
xFE00
KBSR
15
KBDR
11/22/2005
87
xFE04
15
xFE02
DDR
display
0
DSR
0
test
87
0
xFE06
SSST: CS130 F. Hadziomerovic
KBSR[15] = 1; new char in KBDR
DSR[15] = 1 ; DDR is ready for new char.
27
I/O service routines
15 14
0
START
xFE00
KBSR
15
87
0
KBDR
xFE02
15 14
A
B
; input service routine
LDI R1, A
BRzp START
LDI R0, B
BRnzp NEXT_TASK
.FILL xFE00
.FILL xFE02
xFE04
87
0
START
DDR
xFE06
ECHO
KBSR[15] = 1; new char in KBDR
DSR[15] = 1 ; DDR is ready for new char.
11/22/2005
A
B
0
DSR
15
START
; output service routine
LDI R1, A
BRzp START
STI R0, B
BRnzp NEXT_TASK
.FILL xFE04
.FILL xFE06
KBSR
KBDR
DSR
DDR
;keyboard echo
LDI R1, KBSR
BRzp START
LDI R0, KBDR
LDI R1, DSR
BRzp ECHO
STI R0, DDR
BRnzp NEXT_TASK
.FILL xFE00
.FILL xFE02
.FILL xFE04
.FILL xFE06
SSST: CS130 F. Hadziomerovic
28
LC-3 keyboard input routine
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
Start
L1
Loop
L2
Input
L3
L4
ST R1, SaveR1
ST R2, SaveR2
ST R2, SaveR2
LD R2, Newline
LDI R3, DSR
BRzp L1
RTI R2, DDR
LEA R1, Prompt
LDR R0, R1, #0
BRz Input
LDI R3, DSR
BRzp L2
STI R0, DDR
ADD R1, R1, #1
BRnxp Loop
LDI R3, KBSR
BRzp Input
LDI R0, KBDR
LDI R3, DSR
BRzp L3
STI R0, DDR
LDI R3, DSR
BRzp L4
STI R2, DDR
LD R1, SaveR1
LD R2, SaveR2
LD R3, Save R3
BRnzp Next_Task
11/22/2005
; save registers
;loop until display ready
;display newline
;wait for monitor ready
;write next prompr char.
;wait for char
;get input char
;wait for monitor
;display char
29.
30.
31.
32.
33.
34.
35.
36.
SaveR1
SaveR3
DSR
DDR
KBSR
KBDR
Newline
Prompt
.BLKW
1
.BLKW
1
.FILL
xFE04
.FILL
xFE06
.FILL
xFE00
.FILL
xFE02
.FILL
x000A
.STRINGZ
“Input a character>”
Critique:
Loops L1, L2, L3, L4 wait until display ready.
Loop Input waits until char available – gross.
For instance 1 char per sec means wait of
1 million instruction executions – waste of
computer time.
Solution: interrupt: processor is interrupted
only when the character is ready. Generally
processor is interrupted when peripheral device
needs service.
;wait for monitor
;move cursor to new line
SSST: CS130 F. Hadziomerovic
29
Interrupt
PL2
PL1
15 14 13
KBSR
0
15 14 13
xFE00
0
DSR
xFE04
Other device priorities
Priority decision
PL of running program
Jump to ISR
Interrupt line to processor
running program
Interrupt is tested before every FETCH
cycle. If interrupt priority is larger than
running program priority Interrupt is
granted:
1. PC and PSR are saved on stack and
jump is made to interrupt service routine.
2. Interrupt service routine must end up
with RTI (Return from Interrupt) instruction
which loads PC and PSR back from the
stack.
11/22/2005
interrupt
running program
SSST: CS130 F. Hadziomerovic
ISR
(Interrupt
Service
Routine)
RTI
Return from ISR
30