Transcript Diapositive 1

irfu
saclay
3D-MAPS Design
IPHC / IRFU collaboration
Christine Hu-Guo (IPHC)
Outline

3D-MAPS advantages

Why using high resistivity substrate

3 types of 3D-MAPS design
Using 3DIT to improve MAPS performances
3DIT are expected to be particularly beneficial for MAPS :



Combine different fabrication processes
Resorb most limitations specific to 2D MAPS
Split signal collection and processing functionalities, use best suited technology for
each Tier :




Tier-1: charge collection system  Epitaxy (depleted or not) ultra thin layer  X0 
Tier-2: analogue signal processing analogue, low Ileak, process (number of metal layers)
Tier-3: mixed and digital signal processing
Tier-4: data formatting (electro-optical conversion ?)
3D - MAPS
2D - MAPS
Pixel Controller, CDS
Pixel Controller,
A/D conversion
Diode
Diode
digital process (number of metal layers)
feature size fast laser driver, etc.
30-40 µm

Digital
Analog
~< 50 µm
Analog Readout Analog Readout
Circuit
Circuit
Sensor
Diode
Diode
Analog Readout Analog Readout
Circuit
Circuit
~ 20 µm
11-14/10/2009

TSV

Radiation hard
Cluster  S/N
Sensor tier = MAPS  integration 1st level amplification
Ecole microélectronique de l'IN2P3
IRFU - IPHC [email protected]
2
High resistivity sensitive volume  faster charge collection

Exploration of a VDSM technology with depleted (partially ~30 µm) substrate:


Project "LePix" driven by CERN for SLHC trackers (attractive for CBM, ILC and CLIC Vx
Det.)
Exploration of a technology with high resistivity thin epitaxial layer

XFAB 0.6 µm techno: ~15 µm EPI ( ~ O(103).cm), Vdd = 5 V (MIMOSA25)
 Benefit from the need of industry for improvement of the photo-sensing
elements embedded into CMOS chip
TCAD Simulation (by A. DOROKHOV)
15 µm high resistivity EPI compared to 15 µm standard EPI
For comparison: standard CMOS
technology, low resistivity P-epi
high resistivity P-epi: size of depletion
zone size is comparable to the P-epi
thickness!
11-14/10/2009
Ecole microélectronique de l'IN2P3
IRFU - IPHC [email protected]
3
MIMOSA25 in a high resistivity epitaxial layer
Landau MP (in electrons) versus cluster size
0 neq/cm²
0.3 x 1013 neq/cm²
1.3 x 1013 neq/cm²
3
16x96
Pitch 20µm
MIMOSA25




x 1013 neq/cm²
saturation -> >90 % of charge is collected
is 3 pixels -> very low charge spread for
depleted substrate
To compare: «standard» non-depleted EPI
substrate: MIMOSA15 Pitch=20µm, before and
after 5.8x1012 neq/cm2
20 μm pitch, + 20°C, self-bias diode @ 4.5 V, 160 μs read-out time
Fluence ~ (0.3 / 1.3 / 3·)1013 neq/cm2 
Tolerance improved by > 1 order of mag.
Need to confirm det (uniformity !) with beam tests
11-14/10/2009
Ecole microélectronique de l'IN2P3
IRFU - IPHC [email protected]
4
IPHC 3D-MAPS: Self Triggering Pixel Strip-like Tracker (STriPSeT)

Combine Tezzaron/Chartered 2-tiers process with XFAB high resistivity EPI process
Tier-1
Tier-2
Cf~10fF
Tier-3
off <10 mV
G~1
Digital RD
Cc=100fF
Vth
Cd~10fF
Ziptronix
(Direct Bond Interconnect, DBI®*)

Tezzaron
(metal-metal (Cu) thermocompression)
DBI® – Direct Bond Interconnect, low temperature CMOS compatible direct oxide bonding with scalable
interconnect for highest density 3D interconnections (< 1 µm Pitch, > 10 8 /cm² Possible)
W. DULINSKI, A. DOROKHOV, F. MOREL, G. BERTOLONE, X. WEI, …

Tier-1: XFAB, 15 µm depleted epitaxy  ultra thin sensor!!!





Depleted  Fast charge collection (~5ns)  should be radiation tolerant
For small pitch, charge contained in less than two pixels
Sufficient (rather good) S/N ratio defined by the first stage
“charge amplification” ( >x10) by capacitive coupling to the second stage
20 µm
Tier-2: Shaperless front-end: (Pavia + Bergamo)



Tier 2
Single stage, high gain, folded cascode based charge amplifier, with a current source in the feedback loop
 Shaping time of ~200 ns very convenient: good time resolution
Low offset, continuous discriminator
Tier-3: Digital: Data driven (self-triggering), sparsified binary readout, X and Y projection of
hit pixels pattern

11-14/10/2009
Matrix 256x256  2 µs readout time
Ecole microélectronique de l'IN2P3
IRFU - IPHC [email protected]
5
IPHC 3D-MAPS

Delayed R.O. Architecture for the ILC Vertex Detector

Try 3D architecture based on small pixel pitch, motivated by :




Single point resolution < 3 μm with binary output
Probability of > 1 hit per train << 10 %
12 μm pitch :
•
sp ~ 2.5 μm
•
Probability of > 1 hit/train < 5 %
Readout
~1 ms
~200 ms
~1 ms
Split signal collection and processing functionalities :


Tier-1: A: sensing diode & amplifier, B: shaper & discriminator
Tier-2: time stamp (5 bits) + overflow bit & delayed readout
A
Tier 1
Detection diode
or Q injection
Amplifier
12 µm
Acquisition
NMOS only
12 µm
Tier 2
B
TS & R.O.
Amp.+Shaper
Discriminator
Hit identification
+
5 bits (7?) Time Stamp
2nd hit flag
Delayed Readout
future
24 µm
ASD
Detection diode
& Amp
Y. FU, A. BROGNA, A. DOROKHOV, C. COLLEDANI, C. HU, …
 Architecture prepares for 3-Tier perspectives : 12 µm
11-14/10/2009
Ecole microélectronique de l'IN2P3
IRFU - IPHC [email protected]
6
IRFU & IPHC 3D-MAPS: RSBPix

FAST R.O. architecture aiming to minimise power consumption
Subdivide sensitive area in ”small” matrices
running INDIVIDUALLY in rolling shutter mode
 Adapt the number of raws to required frame r.o. time
 few µs r.o. time may be reached (???)

Vrst
Vclp1+Vth
CS
Av
~4
Clamp
Vclp2
CS
Clamp0
Vclp2
Vclp2
CS
Clamp1
Clamp4
Digital Memory
and
Latch
MOSCAP
(100fF)
PWRON_A
MOSCAP
MOSCAP
(20fF)
PWRON_D
PWRON_D
Digital Readout
Vclp2
Track Latch
Discriminator
LATCH_D
Tier-2
Tier-1: NMOS only
Y. DEGERLI, W. DULINSKI, …


DREAD
(Tier-1)
Planned also to connect this 2 tier circuit to XFAB detector tier
20µm
Building Blocks: PLL, 8b/10b, Bias DAC, Pre-Amplifier, Buffer….
11-14/10/2009
Ecole microélectronique de l'IN2P3
IRFU - IPHC [email protected]
7