Transcript No Slide Title

Introduction to PALs
Programmable Array Logic
CSET 4650
Field Programmable Logic Devices
Dan Solarek
Programmable Array Logic (PAL)
Developed by John Birkner & Hua-Thye Chua
Monolithic Memories, Inc.
1976
Used to implement functions in Boolean equation
form
(Recall PROM used tabular form)
More efficient use of IC real estate
Developers continued into FPGAs
Co-founders of Quicklogic
2
Programmable Array Logic (PAL)
AND array inputs are programmable
OR array connections are fixed
The output of each AND gate is permanently
connected to an OR gate
Product terms cannot be shared by OR gates
Simplified PAL block diagram:
Fixed
Connections
3
PAL Block Diagram
A more realistic block diagram of a PAL
would show multiple inputs and outputs
Inputs
Dense array of
AND gates
Product
terms
Dense array of
OR gates
Outputs
4
PAL Architecture: Simplified
Inputs are available in both
true and inverted form
Multiple input AND gates
Each OR gate has a
specific number of
product terms as fixed
inputs
Outputs from OR gates
5
Using PALs: An Example
x1
x2
x3
Implement the following:
f1  x1x2 x' 3  x'1 x' 2 x3
f2  x'1 x' 2  x1x2 x3
P1
P2
P3
P4
AND plane
6
Using PALs: An Example
x1
x2
x3
P1
P2
f1  x1x2 x' 3  x'1 x' 2 x3
f2  x'1 x' 2  x1x2 x3
P1
P2
P3
P4
f1
P3
P4
AND plane
f2
7
PAL Architecture: More Realistic
Six (6) inputs are
available in both true
and inverted form
Twelve (12) input
AND gates
Each OR gate has a
four (4) product terms
as fixed inputs
Four (4) outputs
8
PAL Architecture: More Realistic
The fact that the AND
array is programmable
makes it possible for
these devices to have
many inputs
The fact that the OR
array is fixed makes
the devices small
(which means less
expensive) and fast
9
PAL Architecture
An actual PAL device
PAL16L8
32 input AND gates
up to 8 output functions
See Figure 7-24 in the
Sandige book
10
PAL Outputs Can Be Latched
Typical PALs have:
from 10 to 20 inputs
from 2 to 10 outputs
from 2 to 8 AND gates driving each OR gate
often include D flip-flops
Select
Enable
f1
Flip-flop
D
Q
Clock
To AND plane
MUX output is “fed back” to the AND plane.
11
Understanding the PAL Diagram
A portion of the Realistic PAL diagram shown earlier
12
Understanding the Diagram
D
J
P
Horizontal Lines indicate a product term. Vertical lines provide
True and Complemented forms of external inputs.
Although product terms appear to have only one input, it actually
has 2*n inputs, for n external inputs.
13
PAL Product Terms
B B’A A’ C C’ D D’ I I’ J J’ E E’ F F’ K K’GG’H H’
This looks like an AND gate with one input. It is actually
many more:
B
B’
A
A’
Drawn with a
C
single line (above)
C’
to save space.
P
H
H’
14
Fuse Points
D
J
P
A cross over of a Vertical input line and a horizontal product
term line is a FUSE LOCATION. When the PAL is in its blank
or erased state, all FUSES are connected. This means that each
product term implements the equation:
( A A’ B B’ C C’……. KK’) which will be ‘0’! This means that
the output will be high!
15
PAL Programming
D
J
P
To program, we will BLOW most of the fuses (break the
vertical/horizontal crossover connection). To indicate a logic
function, will use an ‘ X ‘ over a fuse will be kept INTACT.
Will mark intact fuse location
When a fuse is blown, that product term input acts as a permanent
logic ‘1’ so that the input no longer effects the product term.
16
An Example: P’ = D + J’
J
D
P
When implementing an equation, sometimes will not want to
use all available product terms. If ALL fuses along product
term are left intact, then product term value will be ‘0’ and
will not affect equation. Mark unused AND gates by placing
an X over them as shown.
17
Example Product Term AC’H’
B B’A A’ C C’ D D’I I’ J J’ E E’ F F’ K K’GG’H H’
P
The connections will be:
1
1
A
1
1
Actually, fuses are not
C’
‘blown’ in eraseable
PLDs - the connection
is broken in a nondestructive way.
1
H’
Fuse blown
Fuse blown
Fuse intact
Fuse blown
Fuse blown
Fuse intact
P
Fuse blown
Fuse intact
18
Another Example
A
B
C
G
H
I
D
J
P
P’ = A’BGH’ + CD’ + HIJ + BG’H
19
Alternative PAL Diagrams
Implements sum-ofproducts expressions
Four external inputs (and
complements)
Feedback path from
output F1
Product term connections
made via fuses
20
Implementing a Function
Consider implementing the
following expression:
x x x
x xx
x
x
I1 I2 I3 + I2’ I3’ I4 + I1 I4 = F1
Note that only functions of up
to three product terms can be
implemented
larger functions need to be
chained together via the
feedback path
21
Example 7-12 from Sandige
10 primary inputs
8 outputs, with 7 AND gates per
output
1 AND used for 3-state enable
6 outputs available as inputs
more inputs, at expense of outputs
Note inversion on outputs
output is complement of sum-ofproducts
newer PALs have selectable
inversion
Figure 7-24
22
PAL Output Macrocells
4 to 1 MUX
00 = registered active low
01 = registered active high
10 = comb. active low
11 = comb. active high
2 to 1 MUX
Output feedback
External input
23
PAL Output Macrocells
Registered mode
24
PAL Output Macrocells
combinational mode
25