Transcript Document

SST-1 Data Acquisition &
Control
H D Pujara
Institute for Plasma Research
[email protected]
Institute for Plasma Research
Plan of the Talk
Brief Introduction of SST-1
Objective of data acquisition and Control
Timing System
PXI & CAMAC based Data Acquisition system
Major Constituents of Control systems
Software aspects
Indian
Tokamaks
ADITYA
SINP
0.75 m
0.25 m
1.50 T
250 kA
250 ms
Circular
Poloidal Limiters
0.30 m
0.075 m
2.00 T
75 kA
20-30 ms
Circular
Poloidal
Copper Water cooled
Ohmic Transformer
Copper
Ohmic
(Air Core)
Vessel with Electrical break
(Iron Core)
Conducting
Indigenous
M/S Toshiba,
1989
1987
Tokamak
Major Radius
R0
Minor Radius
a
Toroidal Field
BT
Plasma Current
Ip
Pulse Duration

Plasma Cross-section
Configuration
Limiters
Coils Type (TF & PF)
Current Drive & Heating
transformer
Vacuum vessel
Shell
Design & Fabrication
Japan
Installation
SST1 MACHINE PARAMETERS
MAJOR RADIUS
MINOR RADIUS
ELONGATION
TRIANGULARITY
TOROIDAL FIELD
PLASMA CURRENT
ASPECT RATIO
SAFETY FACTOR
AVERAGE DENSITY
AVERAGE TEMP.
: 1.1M
: 0.2 M
: 1.7-2
: 0.4-0.7
: 3T
: 220 kA.
: 5.2
:3
: 1X 1013cm-3
: 1.5 keV
PLASMA SPECIES
: HYDROGEN
PULSE LENGTH
: 1000s
CONFIGURATION
:
: DOUBLE NULL
: POLOIDAL DIVERTER
HEATING & CURRENT DRIVE:
LOWER HYBRID
: 1.0 MW
NEUTRAL BEAM
: 0.8 MW
ICRH
: 1.0 MW
TOTAL INPUT POWER : 1.0 MW
FUELLING
: GAS PUFFING
ISOMETRIC CUT- VIEW OF SST-1
SST-1
VACUUM SYSTEM
CRYOSTAT
MAGNET SYSTEM
CRYGENIC SYSTEM
SUPERCONDUCTING
MGNETS
VACUUM VESSEL
TF MAGNETS
16 SUPER CONDUCTING
SUPPORT STRCTURE
LIQUID NITROGEN SYSTEM
MACHINE SUPPORT STRUCTURE
LIQUID HELIUM SYSTEM
CENTRAL SUPPORT STRUCTURE
PFMAGNETS
9 SUPERCONDUCTING
LN2 PANELS AND SHEILDS
TF SUPPORT STRUCTURE
COPPER MAGNETS
AUXILARY HEATING SYSTEM
OUT SIDE COILS
ICRH
OHMIC TRANSFORMER
VERTCAL FIELD COIL
VF1, 1 PAIR OF COILS
TR2
TR3
ECRH
NBI
TR1 OR CENTRAL SOLENOID
INVESSEL COILS
DIAGONATICS
DATA AQUISISION AND CONTROL
RADIAL AND VERTICAL
CONTROL COILS
PF6 MAGNET
POWER SUPLY
MACHINE PARAMETERS
MAJOR RADIUS = 1.1m
MINOR RADIUS = 0.2 m
ASPECT RATIO = 5.5
ELONGATION = 1.7-2
TRIANGULARITY
TOROIDAL FIELD
= 0.4-0.7
PLASMA CURRENT = 220 kA
PULSE LENGTH
: 1000S
AVERAGE DENSITY = 1X 1013cm-3
AVERAGE TEMP. = 1.5 keV
PLASMA : HYDROGEN
= 3T
Vacuum Subsystem
Vacuum Vassal made up of
16 Wedge shape sections
16 Interconnection ring
• Cryostat
• Pumping system
• Gas Feed System
VACUUM VESSEL MODULE
•
VESSEL SECTOR
•
INTERCONNECTING RING : 1
•
TOP VERTICAL PORT
•
BOTTOM VERTICAL PORT : 1
•
RADIAL PORT
:1
•
RADIAL PORT FLANGE
:1
•
RADIAL PORT BLANKING
FLANGE
TOP PORT
:1
VESSEL RING
:1
VESSEL
SECTOR
RADIAL PORT
: 1
PORT FLANGE
BLANKING
FLANGE
BOTTOM PORT
SST1 CRYOSTAT
Cryostat Parameters:
Vertical Height
: 2.6 m
Outer Diameter
: 4.4 m
Inner Diameter
: 0.355 m
Wall Thickness
: 10 mm
Total Surface Area
: 59 m2
Total Volume
: 39 m3
Total Weight
: 4520 kg
Material
: SS 304L
SST-1 MAGNET SYSTEM
Requirements:
• Confinement, Shaping and Equilibrium
Fields
• Ohmic Flux Storage
• Feed-Back Control
Supercondcting Magnets:
• Toroidal Field (TF) Coils :
Nos.
• Poloidal Field (PF) Coils :
Copper
Nos. Magnets (Water Cooled) :
• Ohmic Transformer (TR) Coils :
Nos.
16
9
7
• Poloidal Field (PF ) Coils ( in-Vessel): 2
Nos.
• Position Control Coils ( in-Vessel)
Nos.
:2
SST-1 Poloidal Field Coils
Design Drivers:
•Support single & double null equilibria with wide range of Triangularity ( 0.40.7), Elongations ( 1.7-1.9), li (0.75 -1.4), p ( 0.01-0.85) & slot divertor
configuration
• Limiter operation during Plasma current ramp up
Parameters of PF Coils
Coil
#
Coil
Vertical
type coils Radius Location
(m)
(m)
PF1
PF2
PF3
PF4
PF5
PF6
1
2
2
2
2
2
0.45
0.45
0.50
1.72
2.01
1.35
0.0
0.43
0.93
1.03
0.65
0.35
Winding
#
Cross- turns
section
(mm2)
71x320
80
71x163
40
136x380 192
85x136
40
85x136
40
100x100 16
Gas feed System
• Plasma of Hydrogen gas
• Gas fueling during normal operation of
1000 sec.
• Uniform gas distribution.
• 28 pizo electric gate valve around the
machine.
• Plasma Density control for constant density
• Online feed control by adjusting gas flow.
Auxiliary Heating system
• Lower hybrid current drive (LHCD) system.
- Responsible for driving the plasma and maintain
current for 1000 sec.
-One Megawatts of CW power at 3.7Ghz
-Two High Power Klystron, each delivering
500KW
- Ohmically driven Ip (110KA to 220Kam) will be
Taken over by LHCD
- Circular plasma will be shaped with PF coils
- Will be lunched through redial port to a grill of 64
wave guides
- Pressured transmission line to avoid the
Breakdown
Ion Cyclotron Resonance Freq.
•
•
•
•
Tetrode based 1.5 MW ICRF system.
Frequency of operation 20 to 92 MHz
Temp of 1.0KeV
Lunched through radial port, four antennas 375Kw
each
• Pressurized 90 meter long & 9 inch dia 50 ohm
transmission line
• Online stub and frequency matching for optimum
power transfer.
• Reflected power will be compensated with hike in
input RF power.
Electron Cyclotron Resonance
Freq. Heating.
• Gyrotron Based 200KW CW @ 84GHz
• Focused Microwave beam of 18 mm
radius.
SST1 ECRH
SYSTEM
Objectives:
• Pre-Ionisation & Plasma start up
• Electron Cyclotron Heating to assist Current drive during LHCD
Main Parameters
• Gyratron Frequency : 82.6 GHz
• Output Power
CW
: 200 kW
• Output Mode
: HE-11
• Operating TF Field :
• Fundamental : 3 T
• 2nd Harmonic : 1.5 T
• Exit dimensions of Waveguide :
63.5 mm
SST-1 LHCD SYSTEM
Frequency
: 3.7
GHz.
Power ( 2 klystrons each of 500 kW CW): 1 MW
Antenna type
: Grill
# of subwaveguides
: 32 x
2rows
Periodicity (with 2mm thick septa)
: 9 mm
Subwaveguide opening
: 76 x7
2
mm
Design NII (at 90o phasing)
: 2.25
NII variation (from 40o to 60o phasing) : 1.0 4.0
Klystron input power
:
10Watt
Plasma Facing Components of
SST-1
Design Drivers:
• Steady state heat and particle
removal
• 1 MW power Input
• Surface temperature  1000 0C
• Baking up to 350 0C
• Electromagnetic forcesss during
VDE, disruptions and halo currents
• Modularity
• Isostatically pressed, low ash
content,Graphite
• Tiles mechanically attached to High
strength copper alloy (CuZr & Cu CrZr)
backplate;
• Cooling tubes (SS304) embedded in &
brazed to the back plates.
PLASMA FACING COMPONENTS OF SST-1
Objective and Requirements of DAS
SST-1 is a steady state device…
The system must capable enough to acquire all required physics information..
Due to continuous nature of operation … no physics information should be lost..
And no unnecessary data should be acquired.
Concept of event for data reduction,
Scheduled and un scheduled events.
If required … must offer lossless acquisition..
Provide support for real time visualization of data.
On line processing for Physics Information.
Remote operation, processing and viewing…
GUI based local and synchronous operations.
Tagged with events for post processing and viewing.
Distributed DAS for batterperformance
data managements
enhancement with growing tech
How SST-1 DAS Differs
Most of the Tokamak operates in pulse mode
Discharge duration could be few seconds
Captures data during discharge.
Retrieves it later on for analysis
Display of data as a single trace.
Do not demand any need of viewing data during discharge
since discharge is limited for few seconds
Generates manageable data during shot-10Mb or so
However SST1 will be operated under steady State for 1000 Seconds
Demands online viewing 1000 seconds
20 minutes, can’t wait till end of the pulse
Online processing to infer physics parameter like
Density, Plasma current
Demands large local buffers for storage
Generates large amount of data
Demands transfer to host-as fast as possible for loss less
acquisition
Storage for post processing
Tagging of events and time
These all puts significant effect on acquisition instruments
Above requirements poses many Technical
problems
Large amount of data
Network load increases substantially
Storage requirements grows enormously
Processing needs also grows and demands faster CPUs
Large buffers or Multi buffer schemes
Deterministic nature of network and minimum latency
Here the root cause is LARGE AMOUNT OF DATA
How one can reduce the data? – EVENT DRIVEN
SAMPLING
Acquire data at lower sampling rate during low activity period
Change Sampling rate as and when important event occurs
Revert-back to normal sampling rate after /\ t
If everything is sequential and pre determined
---window based acquisition
Event driven sampling
How much reduction in data one can achieve in Event
base triggering?

Depends on number of events, duration of events.

Sampling rate during event.

Base level Sampling rate.

Depends on diagnostic and its needs.
What are the problems caused by event driven sampling
Scheme?
Each diagnostic has to identify the events, its duration and required Sampling rate.

Each sub-system like NBI, LHCD, ICRH etc. Has to identify events.

Generation of events- Electronics hardware.
Encoding of events- numbering of events.
 Distribution of events to various sub-systems and digitizers,
Its Time criticality .


Selection of digitizer which can accepts such events triggering.

Time tagging of events while storing the data.

Event recording- Sampling rate, event etcs needs to be stored for post archival.
This basically demands a very unique
timing/triggering system.
Employ various diagnostics to study the various parameters like
Electron Density
Bolo meters
Soft X-Ray radiation
Charge-exchange
Langmiur Probes
Thomson scattering
Plasma Current
Microwave Interferometer
Loop Voltage
Spectroscopy
Electron Temperature
S.N
DIAGNOSTICS
1
Mirnov coils
No. of
channels
Sampling
Freq
Type of
Acquisition
44
1Mhz
Event based
Diagnostics and Events
100ms Multiple window
# Current Ramp up
2
Two component Magnetic
probes
48
Halo Rogowski
coils
50
10KHz
Remarks
100ms Multiple window
# Current Ramp up
# LHCD / NBI ON
# Gas puff/ Pellet
# Current ramp down
or Disruption
Continuous
Control + Daq
1Mhz
Event Based
100ms multiple windows
# Z-position(thres)
# Disruption
16
1 kHz
Continuous
control + DAQ
4
10KHz
Continuous
control + DAQ
10KHz
Continuous
control + DAQ
Continuous
control + DAQ
# LHCD / NBI ON
3
# Gas puff
4
Saddle loops
5
Rogowski coils
6
Fiber optics Current
sensor
2
7
Voltage Loops
24
8
Diamagnetic Loops
4
10KHz
Continuous
Monitor + DAQ
9
Hall sensors
24
10KHz
Continuous
Control + DAQ
10
Bolometer System
10
20
100Hz
20KHz
Continuous
Continuous
# Current ramp down
# Disruption
10KHz
11
SXR Imaging System
10
125
100Hz
1Mhz
Continuous
Event Based
12
HXR
Tomography
10
100
100Hz
1MHz
Continuous
Event Based
Sodium Iodide (NI)
2
5
100Hz
1MHz
Continuous
Event Based
2
5
10KHz
1MHz
Continuous
Event Based
13
14
VUV Broadband
15
FIR interferometer
24
10KHz
Continuous
16
Spectroscopy
12
8
10KHz
1MHz
Continuous
Event Based
17
ECE Radiometer
16
8
1KHz
1Mhz
Continuous
Event Based
18
Langmuir Probes
32
64
10KHz
1MHz
Continuous
Event Based
19
Michelson @
Interferometry
Charge Exchange
20
8
Monitor + DAQ
100ms multiple windows
# NBI ON (L-H trans & H mode)
# Gas puff/pellet
# Disruption
100ms multiple windows
# NBI ON (L-H trans & H mode)
# Gas puff/pellet
# Disruption
100ms multiple windows
# NBI ON (L-H trans & H mode)
# Gas puff/pellet
# Disruption
100ms multiple windows
# NBI ON (L-H trans & H mode)
# Gas puff/pellet
#Digital
Disruption
Counts
100ms multiple windows
# NBI ON (L-H trans & H mode)
# Gas puff/pellet
# MARFE / DP
# Disruption
100ms multiple windows
# NBI ON (L-H trans & H mode)
# Gas puff/pellet
# MARFE / DP
# Disruption
100ms multiple windows
# NBI ON (L-H trans & H mode)
# Gas puff/pellet
# MARFE / DP
# Disruption
S.N
Diagnostics and Data Volume
DIAGNOSTICS
No.
of
chann
els
1 Mirnov coils
2 Two component
Magnetic probes
3 Halo Rogowski
coils
4 Saddle loops
5 Rogowski coils
6 Fiber optics
Current sensor
7 Voltage Loops
8 Diamagnetic
Loops
9 Hall sensors
10 Bolometer
System
11 SXR Imaging
System
48
12 HXR
10
Tomography
13 Sodium Iodide
(NI)
14 VUV Broadband
16
4
2
24
4
24
10
10
Type
Sampling Bytes/ Durat Mbytes
of
Freq
Sample ion
Acqui KHZ
Sec
sition
44 Event
based
Conti
nuous
50 Event
Based
Conti
Conti
Conti
nuous
Conti
Conti
nuous
Conti
Conti
20 Conti
Conti
125 Event
Based
Conti
nuous
100 Event
Based
2
Conti
nuous
5 Event
Based
2
Conti
nuous
1000
10
1000
1
0.5
2 1000
1
960
0.5
1
10
10
2 1000
2 1000
2 1000
32
80
40
10
10
2 1000
2 1000
480
80
2
2
2
2
1
1000
1000
1000
1000
0.5
480
2
2 1000
2
10
0.1
20
0.1
1000
0.1
1000
0.1
1000
10
1
1
5
63
5
50
5
2.5
5
0.4
0.5
2 1000
25
2
0.5
2 1000
No
of
Ev
ent
s
22
5
40
Total of 250 Data channels demanding
Continuous Acquisition for all 1000 sec.
@ 10Khz sampling
Generate 3.5 Gbytes of data.
Generate 3.5 Mbytes/sec
Total of 450 Channels at fast sampling rate @1Mhz, event based…
Number of schedule and unscheduled events about 5
Total Data 225 Mbyte on board
timing/triggering system
Timing System
SST-1 is consists of various subsystems
Subsystems are Physically wide apart.
Time synchronization between the subsystem is required for
proper and reliable operation of Experiment.
Exchange of events between sub systems is essential for
smooth operation. Deterministic distribution within 5 micro sec
Common clock reference for tight simultaneity
between subsystem and central control.
Event based sampling to limit data volume and
not to lose the physics information.
Constituents of Timing system
Master Control Unite (Event Sequencer & distributor)
VME based CPU
Fiber Optic communication Link @100Mbits/sec
Tree Structure
Event Encoder Module
8 Event Inputs
16 bit code
Fiber optic link with master unit
Timer Module
Event Decoder
Programmable Delay & Trigger generators.
Reference Clock
Fiber optic link with master unit
Available BUS Options
ISA 8bit, 16 bit, Max 8MB/s Limitation of slots
PCI 32Bit, 132Mbyte/sec
CPCI 32Bit 64Bit 132/256MB/s
PXI Extension of PCI, Sync. Clock, Trigger lines, Local Bus
EMI/EMC, Cooling, Pug & Play, VISA
VME 32/64Bit, 40/80MB
VXI 32Bit, 40MB/s 10MHz sync clock, Trigger lines, Local
Bus, Module ID, Resource manager, EMI/EMC
IEEE1934 Serial Bus, 200/400Mbits
CAMAC
Available BUS Options For Instrumentations
ISA 8bit, 16 bit, Max 8MB/s Limitation of slots
PCI
32Bit, 132Mbyte
CPCI 32Bit 64Bit 132/256MB/s
PXI Extension of PCI, sync. Clock, Trigger lines, Local Bus
EMI/EMC, cooling , P & P VISA
VME 32/64Bit, 40/80MB
VXI 32Bit, 40MB/s 10MHz sync clock, Trigger lines, Local
Bus,Model ID, P & P, Resource manager EMI/EMC , VISA
IEEE1934 Serial Bus, 200M/400Mbits
CAMAC
What is the solution Considering the data rate generation as per the
requirements
For Slow Diagnostics Demanding Continuous Loss less acquisition.
Volume of data generation is less per sec
FIFO/Dual Ported RAM buffer
Fast back plane
Data streaming to disk
For Fast Diagnostics demanding higher sampling rate
Data must be stored on Onboard Memory
Multi Buffer or Segmented memory for different events
Opted for
Fast Diagnostics: CAMAC based stand alone system
has been chosen. For this a ISA bus based 16 Bit Crate
Controller and a special digitizer supporting multiple
segments of memory for Events has be developed in house.
PXI for Slow Diagnostics: The PXI based system has been
chosen. The major reason of choosing PXI is that it is based on
the industry standard PCI bus. For making it perfect for
instrumentations, the additional trigger lines, local bus and a
clock signal has been incorporate. In addition the chassis complies
with EMC/EMI standard. All the PXI module comes bundled
with Plug and Play driver for windows platform. The bus offers
a transfer rate of 132Mbytes @33MHz & Fiber optic link to host.
Opted for
CAMAC based- Computer Automated
Measurement And Control.
Fast Diagnostics
PXI for Slow Diagnostics
Data Streaming to the disk
VME For control applications
PCI bus
• PCI bus developed by Intel.
• Introduced in 1993.
486 motherboards use PCI as well.
• Clearly is the Bus of the ‘future’
PCI Highlights
• 32-bit bus that normally runs at a maximum of 33
MHz
• Greater system performance ,with a maximum
data transfer rate of 132MB/s
• Offers excellent expandability for highperformance peripheral devices
• investment spanning multiple CPU generations
• Processor independent
Computer Bus Architecture
CPU
RAM
local bus (32-bit)
PCI Bridge
32-bit
32-bit
PCI bus
Hard drive
Video
ISA bridge
16-bit
ISA Slot
PCI Slot
PCI bus
33 MHz, 32-bit, address
lines and data lines are shared
– Memory (where cards live)
– IO (chip connection)
– Configuration
• Bios on bootup
16 15
31
0
Device ID
Vendor ID
Status
Command
Class Code
BIST Header
Latency
Rev
Cache
Base Address Registers
• Each slot on the PCI bus
has the configuration registers
shown at the right.
Cardbus CIS Pointer
Subsystem ID
SubVendor ID
Expansion ROM Base Address
Reserved
Reserved
MaxLat
MinGnt
Int Pin
Int Line
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
The PCI bus
• Wide Industry Support
• Plug and Play capability
• Thousands of software products
• 32-bit data transfers at 33 MHz
(132 Mbytes/sec)
• PCI is a de facto standard
• Automatic Resource Allocation
BIOS will normally "lock" the "PCI IRQ and DMA Settings"
• PCI IRQ and DMA Settings can also be set manually
But limited slots….
1 2 3 4
Peripheral Sizes in PCI and CompactPCI
PXI/CompactPCI
PCI
Half
Size
Full
Size
6U
PCI boards can be redesigned to
fit in PXI/CompactPCI with little
or no electrical changes.
3U
•Eurocard Packaging Proven over decades of
use in industrial applications (VME, VXI, etc.)
Defined by IEEE 1101 Standard
PC Motherboard = Controller +
Backplane
PC Motherboard
with 4 PCI slots
1 2 3 4
CompactPCI
8-slot
Backplane
CompactPCI
Embedded
Controller
1 2 3 4 5 6 7 8
Electrical Extensions
:
Star Trigger
Peripheral
Local
Bus
Peripheral
Peripheral
Star Trigger
Controller
System
Controller
10 MHz
CLK
132 Mb/s, 33 MHz, 32-bit Computer Bus
Trigger Bus
• Integrated 8 Trigger Lines, 10 MHz reference clock, Star Trigger Bus
• Local Bus between adjacent slots 13 lines
Mechanical Extensions
Mandatory Active Cooling
• System-level environmental specifications
for EMC, shock, vibration, and humidity
• Defined embedded controller location
PXI/CompactPCI Form Factors
3U
PXI/CPCI
J2 64-bit PCI and
PXI Features
J1 32-bit PCI
J5
J4
6U
PXI/CPCI
PXI Reserved
PXI Reserved
J3 PXI Reserved
J2 64-bit PCI and
PXI Features
J1 32-bit PCI
6U Adapter Panel
Software Extensions
PXI speeds application development because:
• PXI Controllers MUST support a standard
software framework by including a pre-loaded
OS:
– Windows NT
– Windows 9x
• Peripherals modules MUST be supplied with a
WIN32 Device Driver
PXI and PC Software is Identical
• Operating systems and application software
run unchanged on PXI systems
• Configuration tools recognize PXI modules
as PCI devices
PXI Also Works with Other
Standards
PXI Chassis
VXI or VME Chassis
GPIB INSTRUMENT
GPIB
MXI
CompactPCI
Controller Option
• Embedded controllers
– Most compact solution
– Modular
– Pentium and Pentium III Class
•Remote MXI-3 controllers
–Short or long 200 meter distance
–cupper or fiber connectivity 1.2Gbits/s
can sustain data transfers at over 80 Mbytes/s
–Fully transparent
–Low cost
MXI-3 Benefits
Tem
pe
ratu
re
Flo
w
Con
trol
Pre
ss
ure
Ala
rm
Pan
el
Con
ditio
ns
ST
OP
•
•
•
•
•
More slots for PCs and PXI/CompactPCI
Very high performance serial fiber link 1.2GB/s
Easy to integrate — software transparent
200 meter L O N G distances
Low cost
Front_end Electronics with built in Intelligence for
Plasma Diagnostics.
During operation no entry to hall
Remote setting of front end electronics is required
Signal Originating from
diagnostics has large
dynamic ranges
Dynamic control of
various settings of
Front_end Electronics
Gain, BW
Shielded twisted pair Cables
Opto Isolations
CANBuse base system, multi drop, serial bus @1MBits/s, msg exchange
with priority, priority and address is part of msg,received by all, act if req.
PXI Based Lossless Continuous Data Acquit ion
Platform
Windows2000
Development Tool
LabWindows/CVI
Data Socket based
Client/Server
Architecture
Direct Data
Streaming to
Hard Disk
1.2GB/s Fiber Optic Link
dSampRate = 1200000;
iHalfBufsToRead = iteration ;
GetCtrlVal (panelHandle, PANEL_LST1, &SampRate1);
Server
Architecture
ulCount1 = SampRate1*Num_of_Channel*2;
piBuffer1 = (short *)malloc(ulCount1*2) ;
piHalfBuffer1 = (short *)malloc(ulCount1);
DS_ControlLocalServer (DSConst_ServerLaunch);
Init_DA_Brds (1, &brd1); Init board AI_Configure (1, -1, 2, 10, 0, 1)
DS_Open ("dstp://202.41.112.140/dataport1", DSConst_Write,
DSCallback, NULL, &dsHandle);
DAQ_DB_Config(iDevice1, iDBmodeON)
SCAN_Start(iDevice1, piBuffer1, ulCount1, iSampTB1, uSampInt1, iScanTB1, uScanInt1);
Wihle (loops <100)
STOP
DS_SetAttrValue (dsHandle, "Samp_Rate1", CAVT_FLOAT, &SampRate1, 0, 0);
DAQ_DB_HalfReady(iDevice1, &iHalfReady1,&iDAQstopped);
if ((iHalfReady1 == 1)
DAQ_DB_Transfer(iDevice1, piHalfBuffer1
fwrite (piHalfBuffer1, 2,ulPtsTfr, ffp1);
PlotY (panelHandle, PANEL_GRAPH
DS_SetDataValue (dsHandle, CAVT_SHORT|CAVT_ARRAY
DS_Update(dsHandle);
DS_Open (URL, DSConst_ReadAutoUpdate, DSCallback, NULL, &dsHandle);
DS_EVENT_STATUSUPDATED:
Client
DS_EVENT_DATAUPDATED
hr = DS_GetAttrType (dsHandle, "Samp_Rate1", &type))
If (data type matches)
DS_GetAttrValue (dsHandle, "Samp_Rate1", type, &SampRate1)
DS_GetDataType
If (data type matches
DS_GetDataValue (dsHandle, type, dataArray
Integrate(input_integrater
PlotY (mainPanel, MAINPNL_GRAPH)
Observed Performance of PXI on
Windows2000
Data Acquisition Module with 16 Channels, 12 Bit ADC, supporting aximum1.2Msamaples/sec.
2 channel DAC, 2 Channel of counter/timers and 8 Lines of gital I/O. Such three modules. ( 48
Ch of Analog In, 6 ch of Analog out, 24 I/O nd 6 counter timers)
Continuous Data Acquisition.... Acquisition Server (48 channel @ 10 kHz,
writing to file for 1000 sec. and pushing the all 48 channel on network using
Data Sockets )
Synchronized Continuous Acq. with start trigger (One common start trigger to
module and the same is applied to rest by the back plain)
one
Single Shot application..
On fly sampling rate changing in case of Scheduled Event triggering.
MultiTrigger: In case of event based sampling 100 events with time gap of 70msec can
be acquired with ploting of the data and with out plot the subsequent time gap can be
15msec. (This was tried with pre/post trigger facility
Following performance was very recently
HP Vectra P-III @1.2 GHz supports 96 channels acquisition
@10KHz with pushing all data no network and storing it on hard disk
with few channels plotting on local machine.
Embedded PC of NI P-II @1.2GHz working supports
up 96 channel @20KHz.
This is double the channel handling capacity compare with
PCL machine working at P-III @500MHz
CAMAC based Data Acquisition for fast
diagmnostics
Platform
Windows2000
Development
ToolLabWindows/CVI
Data Socket based
Client/Server
Architecture
On board memory,
Multiple segments
Standalone CAMAC system
Crate Controller
16 bit parallel crate controller
Data transfers under PIO and DMA mode
Device Driver with DAM for Windows2000 platform
Differential line drivers to support the longer distance
ISA bus
CAMAC Digitizer for Fast
Diagnostics
Design our own CAMAC Module
Independent 8 bit ADC per channel, +/- 5 V
Four channel per module
512KB memory per channel
Single width CAMAC module
Digitizing rate up to 1MHz
Selectable pre/post trigger samples
Selectable segment size
Facility for Onfly Reading
Supports Continuous, Transient
and Monitoring Mode
INPUT
SIGNAL
ON FLY
READ BUFFER
HF
CLOCK
GENERATOR
FF
CAMAC
READ
LINES
EF
CLOCK
DIVISION
R
L
A
T
C
H
A
D
C
INSTRUMENTATION
AMPLIFIER
CLK
EN
TRANSIENT
READ BUFFER
W*
CLOCK
Function
CONTINUOUS
READ BUFFER
FIFO
Decoder
CLOCK
SELECTION
HF
START
TRIGGER
SAMPLING
CLOCK
FF
R
B
U
F
1
CLOCK
OR
R
A
M
ENB1
OR
COMPARATOR
NOT
INPUT SIGNAL
CLOCK
DIVISION
ENB2
B
U
F
2
R/W
A0-A14
ADDRESS
COUNTER
CAMAC
WRITE
LINES
L
A
T
C
H
D
A
C
CONTROL LOGIC
CAMAC DIGITIZER
START
RESET
SELECT SAMPLING
RATE
CONTINUOUS MODE
TRANSIENT MODE
MODE
START DIGITIZING
START DIGITIZING
MONITORING
MODE
START TRIGGER
START TRIGGER
START DIGITIZING
STORE DATA IN
FIFO & RAM
READ DATA FROM
FIFO ON LAM
READ DATA FROM
ADC ON-FLY
NO
IS
STOP
TRIGGER
YES
STOP
STOP
IS
STOP
TRIGGER
YES
NO
ON FULL FLAG (FIFO)
READ DATA FROM FIFO
FUNCTIONAL SEQUENCE OF CAMAC
BASED DUAL RATE DIGITIZER
READ DATA FROM RAM
STOP
FOUR IDENTICAL CHANNELS
HF
R
ANALOG
INPUT
CAMAC
INSTRUMENTATION
AMPLIFIER
FIFO
ADC
RAM
READ
BUFFER
LINES
CLK
WR
R/W
CLOCK
ADDRESS
COUNTER
HF
CLOCK
R
CLOCK
GENERATOR
OR
CLOCK
DIVISION
TRIGGER
OR
OR
START
CLOCK
SELECTION
OR
SAMPLING
CLOCK
OR
SAMPLING CLOCK
READ
ACQUISITION
WINDOW
CONTROL LOGIC
HIGH SPEED CAMAC DIGITIZER
Objective and Requirements of
Control
Since SST-1 is consist of many subsystem the major objective is to ensure reliable
and smooth operation.
Provide Integrated interactive Remote control environment
Proper sequencing of subsystem for synchronized operation
Safety interlocks and fail safe measure under normal and abnormal conditions
Fast real time control of Plasma shape and position.
Interactive strategic control during the pulse.
Configuring and downloading operation parameters to various subsystem
Implementation approach
Hierarchical distributed control system.
Supervisory central control at the top Supervising subsystems and
exchanging status , parameters and commands
Individual subsystems are directly controlled and monitored by its
own dedicated intelligent control system
For quicker and faster actions Interlocks and safety measures
will be exercised by individual subsystem
For batter and Efficient managements of the system entire
control activity has been divided in following groups
Machine Control system
Discharge Control System
Diagnostic Control System
Machine Control
All the subsystem doing routine
tasks like monitoring temp,
water flow, vac pressure etc. are
covered under machine control.
Status and heath of all the
subsystem will be monitored
under the Machine control
Down load of limit values and summary of status from subsystem
Power Supply System
Vacuum System
Status of switch Yard
Control of vacuum pumping system,
TF currents on/off,
sequencing gate valves,
limit values,
Partial pressure measurements
TF current profiles
Status of various components
Water Cooling System
Number of cooling system
Discharge cleaning system
for passive plate divertor
On/off,
Copper coils
Discharge currents
OT cooling system
temp
alarm and limit sets
water flow
Cryogenics
status
water pressure etc
Coil Protection and Monitoring system
Status
Auxiliary Heating system
Limit values
Status of LHCD, ICRH, NBI
Dynamic Discharge control System
Due to long discharge time.. One has a option of changing
the strategy online depending upon the situations
Scheduled discharge phases can be dynamically changed…
Includes Plasma Current, Shape, Position and Density Control
Position and Shape Control
Target system PowerPC
Real Time OS….
VxWorks
Position
Control will be fast
Reflective
Memory
Time
scale of
the order of 100 micro sec.
for real time
datainsharing
Changing
current
copper
Plasma Position and Shape Control
conductor active
Common
algorithm to estimate the
feed
back coil
Plasma Position and Shape
Based on Function Parameterization code
Relatively on slow time scale
Constraint due to Super conductor PF Coils
Rapid change of I is not permitted through PF due Quench
And L/R ratio Signal from 48 Mag probes, Plasma Currents ,
Flux loops and coil currents to determine the
shape & Position.
Error in shape will be translated into correction PF current
Real- Time position feedback (Loop back time = 100 us)
Diagnostics
ADC - 96 ch
FIFO
FPDP (160 MB/s)
VM E Bus
RAM
Power Supply
Control
DSP
Processor
LHCD
Control
PCI (132 MB/s)
Reflective
Memory
Reflective
Memory
Real Time Network (13.6 Mbytes/s)
Reflective
Memory
Density and Plasma Current
Control
Electron density
Ref. Density
10ms time scale
Gas Feed
Piezo gate Valve
Controller
Plasma
Microwave
Fringe
Interferometer
Counter
Plasma Current will be controlled
By controlling the LHCD power
Rogowski coils / Hall sensors
1 ms correction time scale
Control Overview
Software & H/W
Platforms….
Windows
Linux
Real-time Linux
VxWorks
Software Development Tools
Lab Windows/CVI
LabView
TCL/TK
MSSQL
ORACLE
EPICS
Hardware
CAMAC
PXI
VME
Reflective Memory
Processor
Pentium
PowerPC
Thanks…….