Transcript Part II

Micro-Controller 8051
Overview
MCS-51 Family Overview
80C51 Family Products

Pin Compatible
DEVICE
Internal Memory
Program Memory
Data Memory
Timer
Interrupt
8031AH
NONE
128x8 RAM
2 x 16 -Bit
5
8051AH
4Kx8 ROM
128x8 RAM
2 x 16 –Bit
5
8051AHP
4Kx8 ROM
128x8 RAM
2 x 16 –Bit
5
8751H
4Kx8 EPROM
128x8 RAM
2 x 16 –Bit
5
8751H-8
4Kx8 EPROM
128x8 RAM
2 x 16 –Bit
5
8751BH
4Kx8 EPROM
128x8 RAM
2 x 16 –Bit
5
8032AH
NONE
256x8 RAM
3 x 16 -Bit
6
8052AH
8Kx8 ROM
256x8 RAM
3 x 16 –Bit
6
8752BH
8Kx8 EPROM
256x8 RAM
3 x 16 –Bit
6
MicroProcessor Part II
2
MCS-51 Family Overview
Architectural Structure of the 8051 Family
COUNTERS
FREQUENCY REFERENCE
OSCILLATOR
&
TIMMING
ROM
/ EPROM
RAM
TWO 16-BIT
TIMER/EVENT
COUNTERS
CPU
64K BYTE BUS
EXPANSION
CONTROL
PROGRAMMABLE I/O
• PROGRAMMABLE
SERIAL PORT
• FULL DUPLEX UART
• SYNCHRONOUS SHIFTER
Int INTERRUPTS
Ext INTERRUPTS
CONTROL
PARALLEL PORTS
ADDRESS DATA BUS
I/O PINS
MicroProcessor Part II
SERIAL IN / SERIAL OUT
3
MCS-51 Family Overview
Internal Block Description
Part
Contents
Interrupt Control
Ext / Internal Interrupts, Masking, Priority
Central Processing Unit
Arithmetic / Logical Operation , Control
RAM
Internal Program Memory
4KB or 8KB : ROM ( = 805X ), EPROM ( = 875X )
Internal Data Memory
4 x 8bit I/O port
4Byte I/O port ( P0 ~ P3 )
Serial Port
Rcv/Snd 1 bit data.
Timer / Counter
Controller - Periodic Operation
Event Counting, Check PulseWidth
Send periodic Interrupt to CPU
ROM
PSEN
(Program Strobe Enable )
ALE (Address Latch Enable)
EA (External Access)
RST ( ReSeT)
External Program Control Signal
Separate Address & Data
0V : Read PRG from External Memory
5V : Read PRG from Internal Memory
Reset port
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MCS-51 Family Overview
Main Features of 8051
Part
Function
Data Bit-Width
8 Bit
Computation
Arithmetic Operation.
Logical Operation
Memory Size
Data – External Memory 64KB , Internal Memory 128B
PGM – External Memory 64KB , Internal Memory 4KB
Communication
Parallel I/O port – 32 ( 4 x 8 Bit )
Serial I/O port – Full Duplex UART
Etc
2 x 16-Bit Timer , Clock Generator
5 Interrupts
UART : Universal Asynchronous Receiver/Transmitter
MicroProcessor Part II
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MCS-51 Family Overview
External Pin Description
/PSEN
ALE
/EA
/RST
Bidirection
I/O Port
RD
WR
T1
T0
INT1
INT0
TXD
RXD
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
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AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Address/Data Bus
Bidirection I/O Port
Bidirection I/O Port
A15
A14
A13
A12
A11
A10
A9
A8
Address Bus
Bidirection I/O Port
6
MCS-51 Family Overview
Executing From External Program Memory
Timing
CLK
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
ALE
/PSEN
PORT2
PORT0
LATCH
Bus Cycle
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MCS-51 Family Overview
Executing From External Program Memory
Structure
P1
P0
8
0
5
1
DATA(AD7~AD0)
EPROM
/EA
A7~A0
Lower Addr.
LATCH
ALE
Addr
Upper Addr. (A15~A8)
P3
P2
/OE
/PSEN
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MCS-51 Family Overview
Executing From External Program Memory
Example
Read
Address 0421h
(87h)
87h
P1
EPROM
P0
8 /EA
0
5
1 ALE
LATCH
Addr
P3
P2
/PSEN
/OE
Upper Address : 04h
Lower Address : 21h
EA : High : Internal Data Memory
EA : Low : External Data Memory
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P0 : Address / Data I/O Port
P2 : Address Bus
9
MCS-51 Family Overview
Executing From External Data Memory
Structure
P1
P0
8
0
5
1
RAM
LATCH
Addr
216
( 0~64KB)
ALE
= 64KB
RD P3
P2
WR
DECODING
MicroProcessor Part II
/CE
WR /OE
10
MCS-51 Family Overview
Executing From External Data Memory
Timing - Read
CLK
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
ALE
PSEN
／ＲＤ
PORT2
PORT0
LATCH
Bus Cycle
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MCS-51 Family Overview
Executing From External Data Memory
Timing - Write
CLK
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
ALE
PSEN
／WR
PORT2
PORT0
LATCH
Bus Cycle
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MCS-51 Family Overview
Instruction Decoder
ACCUMULATOR
TEMP REG
1. Store the OP Code
2. Decoding
3. Output Control Signal
ARITHMETIC
LOGIC
UNIT
DECIMAL
ADJUST
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INSTRUCTION
REGISTER
AND DECODER
CONDITION
BRANCH LOGIC
ACCUMULATOR LATCH
FLAG
INT0
INT1
CARRY
ACC
TIMER
….
…
13
MCS-51 Family Overview
Arithmetic Logic Unit
ACCUMULATOR
Input : 1 or 2 x 8bit data
Output : 8bit result data
1. +, - (carry)
2. Increment, Decrement
3. Bit Complement
4. Rotate Left/Right
5. Nibble Exchange
6. *, /
FLAG
ARITHMETIC
LOGIC
UNIT
DECIMAL
ADJUST
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INSTRUCTION
REGISTER
AND DECODER
CONDITION
BRANCH LOGIC
ACCUMULATOR LATCH
TEMP REG
INT0
INT1
CARRY
ACC
TIMER
….
…
14
MCS-51 Family Overview
Accumulator
ACCUMULATOR
1. Store Input Data
2. Store Result Data
3. Transfer data to
Memory and I/O
FLAG
ARITHMETIC
LOGIC
UNIT
DECIMAL
ADJUST
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INSTRUCTION
REGISTER
AND DECODER
CONDITION
BRANCH LOGIC
ACCUMULATOR LATCH
TEMP REG
INT0
INT1
CARRY
ACC.
TIMER
…
....
15
MCS-51 Family Overview
CPU Timing (I)
Machine Cycle consists of six states ( 12 oscillator periods)
OSC
(xtal1)
ALE
STATE
S1
S2
S3
S4
S5
S6
1-BYTE, 1-CYCLE Instruction (INC a )
READ OPCODE
S2
S3
S4
S5
S6
READ NEXT OPCODE AGAIN
READ NEXT OPCODE ( DISCARD)
2-BYTE, 1-CYCLE Instruction (ADD a , #data )
READ OPCODE
S1
READ NEXT OPCODE
READ 2nd BYTE
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MCS-51 Family Overview
CPU Timing (II)
OSC
(xtal1)
ALE
STATE
S1
S2
S3
S4
S5
S6
S1
S2
S4
1-BYTE, 2-CYCLE Instruction (INC DPTR )
S3
S5
S6
READ
NEXT
OPCODE
AGAIN
READ OPCODE
READ NEXT OPCODE ( DISCARD )
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MCS-51 Family Overview
CPU Timing (III)
OSC
(xtal1)
ALE
STATE
S1
S2
S3
S4
S5
S6
S1
S2
S4
S3
S5
S6
1-BYTE, 2-CYCLE Instruction (MOVX)
NO FETCH
READ OPCODE
NO FETCH
READ NEXT
OPCODE ( DISCARD )
ACCESS EXTERNAL MEMORY
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MCS-51 Family Overview
Memory Organization
Logical Separation of Program and Data Memory
PROGRAM MEMORY
(READ ONLY)
FFFF
DATA MEMORY
(READ/WRITE ONLY)
FFFF
216
Ext
Ext
0FFF
FF
/EA=0
Ext
4KB
=4096B
Int
/EA=1
Int
0000
Int
Int
00
/ RD
/ PSEN
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/ WR
19
MCS-51 Family Overview
Program Memory
 After reset, the CPU begins execution from location 0000h
 The interrupt causes the CPU to jump to that location, where it
commences execution of the service routine
Ex) External Interrupt = 0003h
 The lowest 4K bytes of program memory can be either in the On-chip
ROM or in an External ROM ( /EA (=External Access ))
 The read Strobe to external ROM, /PSEN, is used for all external
program fetches. /PSEN is not activate for internal program fetches.
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MCS-51 Family Overview
Program Memory
Internal Program Memory : Lower 4KB region of the program memory
0FFF
Longer service routines can be jump
instruction
PROGRAM
LOCATIONS
002B
If an interrupt service routine is short
enough ( as is often the case in control
applications), it can reside entirely
within that the 8-byte interval.
0023
001B
INTERRUPT
LOCATIONS
0013
8 BYTE
000B
RESET
0003
0000
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MCS-51 Family Overview
Data Memory
 Internal Data Memory space is shown divided into three blocks, which are generally
refereed to as the lower 128, the Upper 128, and SFR space
 Internal Data Memory Address are always 1 byte wide ( 256Byte )
FF
Accessible by
direct Addressing
UPPER 128
Special Function Registers
80
7F
LOWER 128
Accessible by indirect
Addressing only
PORTS
STATUS BIT
CONTROL BIT
TIMER
REGISTERS
STACK POINT
ACCUMULATOR
(ETC..)
00
Accessible by direct
and indirect addressing
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MCS-51 Family Overview
The Lower 128 Byte of internal RAM
The Lower 128 Byte of internal RAM
BANK
SELECT
BIT IN
PSW
3F ~ 7F
STACK
20 ~ 2F
BIT-ADDRESSABLE SPACE
11
18 ~ 1F
10
10 ~ 17
01
08 ~ 0F
00
00 ~ 07
4 BANKS OF REGISTER (R0~R7)
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MCS-51 Family Overview
4 Banks Of Register
4 X 8 REGISTER BANK
R7
R6
R5
R4
R3
R2
R1
R0
4th REG. BANK
3rd REG. BANK
2nd REG. BANK
R7
R6
R5
R4
R3
R2
R1
R0
1st REG. BANK
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MCS-51 Family Overview
Bit-Addressable Register
7F
7E
7D
7C
7B
7A
79
78
2Fh
77
76
75
74
73
72
71
70
2Eh
Boolean Instruction ( Bit Operation )
AND, OR, CLEAR, SET
COMPLEMENT, MOVE BIT …..
Ex) ANL
CY, Bit Address
CY
Bit Address
ANL
Before :
0F
0E
0D
0C
0B
0A
09
08
21h
07
06
05
04
03
02
01
00
20h
After :
MicroProcessor Part II
AND
CY
CY, 27h.3
CY
1
(27h) 0 0 1 0 1 1 1 0
CY
1
25
MCS-51 Family Overview
Special Function Register (SFR) - (I)
1. Software Control/Operation ( Acc, B, DPTR, PSW, SP )
2. Internal Unit Control
Register
Mnemonic
Internal
Address
Bit/Byte
Access
Port 0 Latch
P0
80
Bit
Stack Point
SP
81
Byte
Data point ( Word )
DPTR
82 ~ 83
Word
Data point Low Byte
DPL
82
Byte
Data point High Byte
DPH
83
Byte
Power Control
PCON
87
Byte
Timer/Counter Control
TCON
88
Bit
Timer/Counter Mode Control
TMOD
89
Byte
Timer/Counter 0 Low Byte
TL0
8A
Byte
Timer/Counter 1 Low Byte
TL1
8B
Byte
Timer/Counter 0 High Byte
TH0
8C
Byte
Timer/Counter 0 High Byte
TH1
8D
Byte
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MCS-51 Family Overview
Special Function Register (SFR) - (II)
Register
Mnemonic
Internal
Address
Bit/Byte
Access
Port 1 Latch
P1
90
Bit
Serial Port Control
SCON
98
Bit
Serial Data Port
SBUF
99
Byte
Port 2 Latch
P2
A0
Bit
Interrupt Enable
IE
A8
Bit
Port 3 Latch
P3
B0
Bit
Interrupt Priority Control
IP
B8
Bit
Program Stats Word
PSW
D0
Bit
Accumulator
Acc or A
E0
Bit
B Regster
B
F0
Bit
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MCS-51 Family Overview
Special Function Register (SFR) - (III) - Software Control/Operation
 Acc : 8 Bit Accumulator ( Arith./Logical Operation)
 B
: General Purpose Register : X , /
 DPTR : 16Bit Register , 8-bit accessable.
( using address pointer in the transmit External Data transfer )
 PSW : 8 Bit -Register,
( carry, Overflow, Parity Flag, Selection of the Register Bank )
 SP
: Stack Point , 8-Bit Register
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MCS-51 Family Overview
Special Function Register (SFR) - (III) - Internal Unit Control
 Timer/Count
: TH1, TL1, TH0, TL0, TMOD, TCON
 Serial Port
: SBUF, SCON, PCON
 Interrupt control
: IE, IP
 I/O Port
: P0, P1, P2, P3
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Chap2 . The Instruction of 8051 Family
Instruction Set
5 Groups - 51 Instructions
1. Data Transfers Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. Boolean Instructions
5. Jump Instructions
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Chap2 . The Instruction of 8051 Family
The Concepts of OPCODE & OPERAND
Instruction Code
1 Byte Instr.
OP Code
+
Operand
(Specification of the Operation)
(Specification of the Address)
The length of an Instruction depends on
1. The number of operands it involves
2. The Way it specifies each operands
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Chap2 . The Instruction of 8051 Family
Some Inst. Formats of the Intel 8085
Single-byte zero address Instruction
Single-byte one address Instruction
Opcode
Operand field 1
Operand field 2
Single-byte two address Instruction
Two-byte one address Instruction
Three-byte one address Instruction
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Chap2 . The Instruction of 8051 Family
 Every general-purpose computer has its own unique instruction.
 The Instruction Code is a group of bits that tell the computer to perform
a specific operation.
 Operation Code
: It define such operations as add, subtract, multiply, shift, and
complement.
Total number of operations obtained determines the set of machine
operations.
Opcode must consist of at least n bits for a given 2n (or less) distinct
operations.
 Instruction (=Macro-Instruction) = The Sequences of Micro-Instruction
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instructions
 1. The Immediate Addressing Mode
 2. The Direct Addressing Mode
 3. The Register Addressing Mode
 4. The Register-Specific Addressing Mode
5. The Register Indirect Addressing Mode
6. The Register Indexed Addressing Mode
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Chap2 . The Instruction of 8051 Family
1.Data Transfer Instruction - The Immediate Addressing Mode
 The Immediate Addressing Mode
: Immediate addressing, or perhaps more explicitly, immediate constant
addressing, refers to the source being a constant embedded into code.
Mov a , #1
; { 74 01h } = { Opcode + Operand }
Include Data
Register(Acc, SFR), Memory
Org
mov
mov
mov
8000h
a, #0h
a, #11h
a, #27
; set the origin
; put 0 into the accumulator
; put 11h into the accumulator
; put 27(Dec) = 1bh into the accumulator
• Start Addressing : 8000h of external RAM
• The sequence of Accumulator : ??h > 00h > 11h > 1bh
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Immediate Addressing Mode
Ex )
MOV A , #33h
MOV DPTR , #1234h
PROGRAM
MEMORY
ACC
PROGRAM
MEMORY
33h
74
33
OP CODE
IMMEDIATE DATA
90
12
34
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DPTR
DPH
DPL
12h
34h
OP CODE
IMMEDIATE DATA
36
Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Immediate Addressing Mode
Ex )
Org
mov
mov
mov
mov
mov
mov
8000h
psw, #0
r0, #0
r1, #1
psw, #8
r0, #0
r1, #1
; set the origin
; select register bank 0
; put 0 into register0
; put 1 into register1
; select register bank 1
; put 0 into register0
; put 1 into register1
Org
mov
mov
8000h
70h, #0
71h, #1
; set the origin
; put 0 into internal register 70
; put 1 into internal register 71
Org
mov
8000h
DPTR, #1234h
; set the origin
; place 12h into DPH and 34h DPL
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Direct Addressing Mode
 The Direct Addressing Mode
: The Direct addressing mode refers to specifying an internal data register
or an SFR by its address.
Org
8000h
; set the origin
mov
a, 70h
; copy contents of internal register 70h to a
mov
a, #0
; clear the accumulator
mov
90h, a
; copy the accumulator contents to SFR 90h
MOV ……. , ……..
Internal Data Memory  Acc, Reg ..
Internal Data Memory  Internal Data Memory
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Direct Addressing Mode
Ex )
mov A , 33h
mov 30h , R7
DATA
MEMORY
33h
ACC
R7
D1
DE
D1
DATA
DATA
MEMORY
DE
30h
DATA
< Instr. Code >
mov A , #33h : 74 33
mov A , 33h : E5 E0
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Direct Addressing Mode
Ex )
mov 30h , 35h
DATA
MEMORY
PROGRAM
MEMORY
85
30
35
mov 06h , 00h
30h
D1
35h
D1
DATA
MEMORY
PROGRAM
MEMORY
DATA
85
06
00
00h
DE
06h
DE
DATA
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Direct Addressing Mode
Ex )
Port 4 equ
0E8h ; port 4
Port 1 equ
090h ; port 1
Org
8000h
; set the origin
mov a, Port4
; copy the contents of port 4 (= E8h)
mov Port1, a
; copy the acc. contents to contents of
port 1
ljmp
8000h
; repeat
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Register Addressing Mode
 The Register Addressing Mode
: The Register addressing mode refers to either the source or the
destination being one of the eight registers of the currently selected
register bank.
MOV PSW, #00010000B
MOV A, #30h
MOV R1, A
MOV R3, #20h
MOV R0, R1
; BANK SELECT (BANK1)
; Immediate Addressing Mode
; R1 = 30h
1010 1011 0010 0000
; REG  REG (X)
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Chap2 . The Instruction of 8051 Family
Cf ) Program Status Word (PSW)
 The PSW contains several status bit that reflect the current
state of the CPU.
CY AC F0 RS1 RS0 OV
PSW7
CARRY FLAG RECEIVES CARRY OUT
FROM BIT 1 OF ALU OPERANDS
PSW6
AUXILARY CARRY FLAG RECEIVES CARRY OUT
FROM BIT 1 OF ADDITION OPERANDS
PSW5
GENERAL PURPOSE STSTUS FLAG
PSW4
REGISTER BANK SELECT BIT 1
P
PSW0
PARITY OF ACCUMULATOR SET
BY HARDWARE TO 1 IF IT CONTAINS
AN ODD NUMBER OF 1S, OTHERWISE
IT IS RESET TO 0
PSW1
USER DEFINABLE FLAG
PSW2
OVERFLOW FLAG SET
BY ARITHMETIC OPERATIONS
PSW3
REGISTER BANK SELECT BIT 0
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Register-Specific Addressing Mode
 The Register-Specific Addressing Mode
: Some instructions are specific to the registers used.
inc
a
; increase contents of accumulator
; 04h
inc
DPTR
; increase contents of DPTR
; A3h
org
8000h
; set the origin
mov
a, #1
; move the contents 1 into the accumulator
mov
0E0h,#1
; move the contents 1 into SFR E0h
ljmp
0
; return to the monitor
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Register-Specific Addressing Mode
mov
a, #1
; move the contents 1 into the accumulator
PROGRAM
MEMORY
“take the following byte and place in the accumulator”
74
01
= the accumulator being the destination is implicitly coded
in the instruction
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Register-Specific Addressing Mode
mov
0E0h, #1
; move the contents 1 into SFR E0h
PROGRAM
MEMORY
the following 2 bytes
75
E0
01
first is the address of register
put the second byte to E0h ( = SFR )
01
E0h
= SFR
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Register Indirect Addressing Mode
 The Register Indirect Addressing Mode
: The address of the source or destination is not given explicitly.
Instead, the contents of a register is used as the target address.
org
8000h
; set the origin
mov
PSW, #0
; select register 0
mov
R0, #78h
; move 78h into register 0
mov
@R0, #1
; set the register whose address is specified in
; the R0 register to the constant 1
ljmp
0
; return to the monitor
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Register Indirect Addressing Mode
mov R0, # 40h
mov A, @R0
DATA
MEMORY
40h
35
mov R1, # 50h
mov @R1, #ADh
Acc
DATA
MEMORY
35
50h
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AD
48
Chap2 . The Instruction of 8051 Family
1.Data Transfer Instruction - The Register Indirect Addressing Mode
mov @R0, 40h
DATA
MEMORY
40h
55
R1
55
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Chap2 . The Instruction of 8051 Family
Addressing Mode - The Source & Destination of MOV Instruction
INTERNAL
DATA
MEMORY
mov 77h, DPL
FFh
7Fh
SFR
mov b, a
80h
00h
mov a, 88h
mov 33h, R7
Acc
mov a, 77h
mov 10h, 77h
mov a, R3
R7
R6
R5
R4
R3
R2
R1
R0
REGISTERs
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Chap2 . The Instruction of 8051 Family
Addressing Mode - The Source & Destination of MOV Instruction
mov 10h, 77h
mov @R1, #33h
mov 33h, R7
mov 3Fh, #33h
Direct
Addressing
Register
R0 ~ R1
Indirect
Addressing
Acc
Immediate
Data
mov a, #33h
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Register Indexed Addressing Mode
 The Register Indexed Addressing Mode
In this mode, the source or destination address is obtained by adding the value
held in the accumulator to the base address. The base address may either be
the data pointer DPTR, or the program counter PC.
Register Indirect Addressing
@ Base Register + Index Register
DPTR, PC
Acc
mov a , @a + DPTR
mov a , @a + PC
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Register Indexed Addressing Mode
mov a , @a + DPTR
mov a , #1
mov DPTR, #1000h
mov a, @a + DPTR
PROGRAM
MEMORY
Acc
3A
DPTR
Acc
1000h
1
+
1EADh
3F
DPTR
PROGRAM
MEMORY
30
31
+
32
1E73
1000
33
Acc
Acc
34
3F
31
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53
Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Register Indexed Addressing Mode
PROGRAM
MEMORY
2000h
74
2001h
10
2002h
83
2003h
2013h
Org
mov
movc
mov
2000h
a , #10h
a, @a + PC
Acc
a , #10h
10h
movc a , @a+PC
Current PC
PC
2003h
+
55h
55
MicroProcessor Part II
54
Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Stack Oriented Data Transfer
 The Stack Oriented Data Transfer
: Another form of register indirect addressing is implemented with push
and pop instructions. These instructions use the SFR stack pointer (SP)
Org
mov
mov
push
mov
pop
8000h
SP , #4Fh
a, #45h
acc
b, #0
b
push
push
acc
a
; set the origin
; initialize stack point
; put 45h in the accumulator
; push the accumulator
; clear the B register
; pop top of stack into the B register
; Note that the operand acc is the symbol define to be 0E0h.
; ( X ) : it uses the register-specific addressing mode.
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Chap2 . The Instruction of 8051 Family
1. Data Transfer Instruction - The Bit Oriented Data Transfer
 The Stack Oriented Data Transfer
 Micro-Controller often manipulates single-bit data signals
 ( Ex ) pushbutton , a motor driver, Bit-Addressable Access)
Org
mov
mov
8000h
C , P1.0
P1.1, C
ljump 8000h
; set the origin
; move the button state into carry flag
; move the carry flag to the LED
; repeat
Vcc
..
..
Architecture
P1.2
P1.1
P1.0
..
..
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Chap2 . The Instruction of 8051 Family
2. Exchange Instruction
 Exchange Instruction
: Exchange Instructions perform powerful two-way data transfers without
the need for a temporary storage byte.
Two Exchange operations :
1. Byte-wise XCH
2. Nibble-wise XCHD (exchange digit)
XCH
a , <Source>
XCHD
a , Ri
R0~R7
@R0,@R1
Direct Address Mode
Acc
Source
@R0,@R1
Acc
Byte
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Source
Nibble
57
Chap2 . The Instruction of 8051 Family
2. Exchange Instruction
XCH
XCH
a , R5
a
R5
Before
15
78
Before
After
78
15
After
XCH
a , 30h
a , @R1
a
@R1
12
34
34
XCHD
a
(30h)
Before
A5
37
Before
After
37
A5
After
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a , @R0
a
@R1
56
78
58
76
58
Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Arithmetic Instructions
 INC/DEC Instruction
: Register-specific, Register, Direct, Register Indirect Addressing
: Loop Counters, Pointers
Mnemonic :
INC Source Operand
DEC Source Operand
INC
: Source Data = Source Data + 1
: Source Data = Source Data - 1
a
Acc
CY
AC
OV
P
Before
FF
--
--
--
X
After
00
--
--
--
0
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Arithmetic Instructions
DEC
a
Acc
CY
AC
OV
P
Before
00
--
--
--
X
After
FF
--
--
--
1
INC
30h
INC
DPTR
DEC
DPTR
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DEC
DEC
DPL
DPH
60
Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Arithmetic Instructions
 ADD/SUB Instructions
a, Source Operand
Acc
Acc
Src Data
2. ADDC a, Source Operand
Acc
Acc
Src Data
CY
3. SUBB a, Source Operand
Acc
Acc
Src Data
CY
1. ADD
Acc, R0~R7
@R0, XXh
#XXh
Multi-Byte Adding
C
16Bit
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C
8Bit
C
8Bit
61
Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Arithmetic Instructions
Ex )
ADD
a, #32h
Before
Acc
76
CY
--
AC
--
OV
--
P
--
A8
--
--
1
0
After
PSW
Sign Bit
0111 0110 (76h)
+ 0011 0010 (32h)
---------------------------1010 1000 (A8h)
Over Flow Flag
(+) + (+ )
-128 ~ + 127
(+)
(+)
Result ( - ) ?
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Arithmetic Instructions
Ex )
ADD
a, @R1
Before
Acc
86
CY
--
AC
--
OV
--
P
--
E8
--
--
0
0
After
@R1 = 62h
Sign Bit
1000 0110 (86h)
+ 0110 0010 (62h)
---------------------------1110 1000 (E8h)
(-) + (+) = (-)
O.K.
(-)
(+)
Result ( - )
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Arithmetic Instructions
Ex )
Before
After
ADDC a, 50h
Acc
55
A3
CY
1
0
Addr 50h = 4Eh
AC
-0
OV
-1
P
-0
0101 0101 (55h)
+ 0100 1110 (4Eh)
+
1
---------------------------1010 0011 (A3h)
Over Flow Flag
-128 ~ + 127
For Multi-Byte Add
Sign Bit
(+)
(+)
(+)
Result ( - )
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Arithmetic Instructions
Ex )
Before
After
ADDC a, R5
Acc
E9
41
CY
0
1
R5 = 58h
AC
-1
OV
-0
P
-0
Sign Bit
1110 1001 (E9h)
+ 0101 1000 (58h)
+
0
---------------------------1 0100 0001 (41h)
Over Flow Flag
-128 ~ + 127
(-)
(+)
(..)
Result (+ )
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Arithmetic Instructions
Ex )
Before
After
SUBB a, @R0
R0 = 37h
Barrow
Acc
53
CY
1
AC
--
OV
--
P
--
1B
0
1
0
0
0 11110
0101 0011 (53h)
- 0011 0111 (37h)
1
---------------------------0001 1011 (1Bh)
(+) - (+) = (+)
O.K.
For Multi-Byte Sub
0110
(+)
(+)
(+)
Result (+ )
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Arithmetic Instructions
 Multiplication Instructions
MUL
AB
B
Acc
MSB
B
Acc
LSB
OV Flag = Set ( if Acc > 255 )
mov
mov
mul
a , #31h
b , #10h
ab
B
03
MSB
; move the 31 into Accumulator
; move the 10 into B register
; Acc X B
Acc
B
Acc
10
10
31
LSB
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Arithmetic Instructions
 Division Instructions
B
DIV
AB
Acc
Result(portion)
Acc
Remainder
/
B
OV Flag = Set ( if B Reg = 0 )
mov
mov
div
a , #118; move the 31 into Accumulator
b , #5
; move the 10 into B register
ab
; B / Acc
B
3
Acc
17
Acc
76
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B
/
5
68
Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Logical Instructions
 Byte-wise Logical Operations
Inst.
ANL
ORL
XRL
ANL
ORL
XRL
CPL
CLR
SWAP
Source
Destination
Acc
,
Direct Addressing ,
R0 ~ R7
@R0, @R1 ..
Direct Addressing
# Data
Acc
# Data
Acc
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Logical Instructions
CLR A
Before
After
CLR A
(CLear Acc )
10110101 b (B5h)
00000000 b (00h)
ANL Dest, Src
CPL A
CPL A
(ComPlement Acc)
Before
After
10110101 b (5Bh)
01001010 b (4Ah)
ORL Dest, Src
ANL 37h , #11110000 b
ORL a , R4
Before
(37h)
# 01110111 b
#11110000 b
Before
(Acc)
(R4)
# 01110111 b
#11110000 b
After
(37h)
#01110000 b
After
(Acc)
#11110111 b
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Logical Instructions
XRL Dest, Src
XRL P1 , #51h
XRL a , @R0
Before
(Acc)
(@R0)
# 10010001 b
# 11100011 b
Before
(P1)
# 01010011 b
# 01010001 b
After
(Acc)
# 01110010 b
After
(P1)
# 00000010 b
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Logical Instructions
RL
Acc
RR
(Rotate Acc Left )
MOV
RL
RL
RL
RL
a , # 37h
a
a
a
a
a =
Acc
(Rotate Acc Right )
MOV
RR
RR
RR
RR
a , # 37h
a
a
a
a
a =
# 73h
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# 73h
72
Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Logical Instructions
RLC
Acc
(Rotate Acc & Carry Left )
RRC
(Rotate Acc & Carry Right )
CY
Acc
CY
Before 1
00011001
0
00110011
After
Acc
CY
Before
After
Acc
CY
1
10011000
0
11001100
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Logical Instructions
SWAP
Acc
(SWAP Acc)
Acc
Before 11000011
00111100
After
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Boolean Instructions
• Bit Operation = Carry Flag ( CY ) = Bit Accumulator
cf) Byte Operation = Accumulator
Bit Operation
CY
Bit Addressable Range
ANL
C, Bit Address
Ex) ANL C, 20h.5
ORL
C, Bit Address
Ex) ORL C, A.7
CPL
C
Bit Address
Ex) CPL C
Ex) CPL 23h.7
SET
C
Bit Address
Ex) SET C
Ex) SET 40h
CLR
C
Bit Address
Ex) CLR C
Ex) CLR 28h.0
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Boolean Instructions
Bit Transfer
MOV
CY
C, Bit Address
Direct Address
Ex) MOV C, 20h.5
Before CY
(20h)
After
MOV
Bit Address, C
0
10101100
CY
1
Ex) MOV 26h.0, C
Before CY
(26h.0)
1
11000010
After
11000011
(26h.0)
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction
Program Counter
 On Power-On-Reset : PC is RESET ( 0000h )
 1 Byte Instruction Fetch : PC = Current PC + 1
 The address pointer of next instruction
Program Flow Control Instructions
1. Branch Instructions
2. Subroutine Calls
3. Interrupts
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Unconditional Jump Instructions
1. Unconditional Jump Instructions
1. SJMP < Realtive Address >
2. AJMP < Address 11 >
3. LJMP < Address 16 >
4. JMP
@A+DPTR
: Short Jump
: Absolute Jump
: Long Jump
: Long Jump ( Indexed Addressing )
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Unconditional Jump Instructions
1. SJMP < Realtive Address >
: Short Jump
Signed 8 Bit (-128 ~ +127)
PROGRAM
MEMORY
051Eh
051Fh
0520h
SJMP 06h
80
06
??
Current PC
0520h
0526h
+
0526h
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Unconditional Jump Instructions
Org 0300h
SJMP BOT
User : JMP
…
RANGE
-128 ~ 127
CAA : MOVE A, R1
…
Compiler
( If Range (-128 ~ 127 ))
…
BOT : INC A
SJMP
….
….
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Unconditional Jump Instructions
2. AJMP < Address 11 >
: Absolute Jump
AJMP 01D2h
083Fh
0840h
0841h
09D2h
21
D2
??
01D2 = 0000 0001 1101 0010
Current PC
0841 = 0000 1000 0100 0001
09D2 <= 0000 1 001 1101 0010
11 Bit Address => Jump range ( ~ 2KB )
Saving 1 Byte ( cf. LJMP : 2 Byte )
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Unconditional Jump Instructions
3. LJMP < Address 16 >
: Long Jump
LJMP 0A3Eh
0056h
0057h
0058h
02
0A
3BYTE
PC : 0A3E
3E
0A3Eh
0A3Fh
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Unconditional Jump Instructions
Org 0300h
LJMP BOT
User : JMP
…
RANGE
~ xxx
CAA : MOVE A, R1
…
Compiler
( If Range :
over -128 ~ 127 )
…
BOT : INC A
LJMP
….
….
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Unconditional Jump Instructions
4. JMP
@A+DPTR
JMP
03A7
: Long Jump ( Indexed Addressing )
@A+DPTR
73
DPTR
Acc
0C
0410
+
PC
041C
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Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Conditional Jump Instructions
2. Conditional Jump Instructions
1. JZ
< Relative Address >
2. JNZ
< Relative Address >
3. JC
< Relative Address >
4. JNC
< Relative Address >
5. JB
< Bit > , < Relative Address >
6. JNB
< Bit > , < Relative Address >
7. JBC
< Bit > , < Relative Address >
8. CJNE
A , Direct , < Relative Address >
9. CJNE
A, #Data , < Relative Address >
10. CJNE
Rn , #Data , < Relative Address >
11. CJNE @Ri , #Data , < Relative Address >
12. DJNZ
Rn , < Relative Address >
13. DJNZ
Direct , < Relative Address >
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:
:
:
:
:
:
:
:
:
:
:
:
85
Chap2 . The Instruction of 8051 Family
2. Data Processing Instruction - Call & Return Instructions
3. Call & Return Instructions
1. ACLL < Address 11 >
2. LCALL < Address 16 >
3. RET
4. RETI
: ( Range : 2KByte )
: ( Range : 64KByte )
: Pop program counter off the stack
: Pop program counter off the stack
: and reset interrupt hardware.
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Chap3. Timer Interrupt & Optimize
Timer Interrupt
0FFF
PROGRAM
LOCATIONS
INTERRUPT
TABLE
RESET
Longer service routines can be jump
instruction
RI+TI
TF1
IE1
TF0
IE0
002B
0023
001B
0013
8 BYTE
000B
If an interrupt service routine is short
enough ( as is often the case in control
applications), it can reside entirely
within that the 8-byte interval.
0003
0000
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Chap3. Timer Interrupt & Optimize
TCON Register
(MSB)
(LSB)
TF1 TR1 TF0 TR0 IE1
NAME
IT1
IE0
IT0
Function
TFx
Timer x over flow Flag
Set by hardware on timer/counter overflow
Cleared by hardware
when processor vectors to interrupt routine
TRx
Timer x Run control bit
Set/Cleared by software to turn timer/counter on/off
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Chap3. Timer Interrupt & Optimize
TCON Register
(MSB)
(LSB)
TF1 TR1 TF0 TR0 IE1
NAME
IEx
ITx
IT1
IE0
IT0
Function
Interrupt x Edge flag
Set by hardware when external interrupt edge detected
Cleared when interrupt processed.
Interrupt 1 Type control bit
Set/Cleared by software to specify
Falling edge/low level triggered external interrupts
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Chap3. Timer Interrupt & Optimize
TMOD Register - Operation Control
(MSB)
GATE
(LSB)
C/T
M1
TIMER1
M0
GATE
C/T
M1
M0
TIMER2
GATE Gating Control
When Set Timer/Counter “x”is enabled
Only while “INTx”pin is high and “TRx” control pin is set
When Cleared Timer “x” is enabled
C/T
Whenever “TRx” control bit is set
Timer or Counter Selector
Cleared for Timer operation (input from internal system clock).
Set for Counter operation (input from “Tx” input pin)
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Chap3. Timer Interrupt & Optimize
TMOD Register - Operating Mode Control (0 , 1, 2 )
(MSB)
GATE
(LSB)
C/T
M1
M0
GATE
TIMER1
M1 M0
C/T
M1
M0
TIMER2
Function
0 0
8048 TIMER : ”TLx” serves as 5-bit prescaler.
0 1
16-bit Timer/Counter : “THx” and “TLx” are cascaded
1 0
“THx” hold a value which is to be
Reloaded into “TLx” each time it overflows
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Chap3. Timer Interrupt & Optimize
TMOD Register - Operating Mode Control (Mode 3)
(MSB)
GATE
(LSB)
C/T
M1
M0
GATE
TIMER1
C/T
M1
M0
TIMER2
Timer
Function
TL0 is an 8-bit timer-counter
Controlled by the standard Timer 0 control bits
Timer 0
TH0 is an 8-bit timer
Only Controlled by Timer 1 control bits (TCON.TR1)
Timer 1
Timer-counter 1 stopped
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Chap3. Timer Interrupt & Optimize
Timer Mode - Mode 0
osc
 12
Timer/Counter 1 Mode 0:13-bit Counter
C /T  0
TL1
(5BITS)
T1 PIN
TH1
(8BITS)
TF1
INTERRUPT
C / T  1 CONTROL
TR1
GATE
INT1 PIN
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Chap3. Timer Interrupt & Optimize
Timer Mode - Mode 1
osc
 12
Timer/Counter 1 Mode 1:16-bit Counter
C /T  0
TL1
(8BITS)
T1 PIN
TH1
(8BITS)
TF1
INTERRUPT
C / T  1 CONTROL
TR1
GATE
INT1 PIN
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Chap3. Timer Interrupt & Optimize
Timer Mode - Mode 2
osc
 12
Timer/Counter 1Mode 2:8-bit Auto-Reload
C /T  0
TL1
(8BITS)
T1 PIN
TF1
INTERRUPT
C / T  1 CONTROL
RELOAD
TR1
TH1
GATE
(8BITS)
INT1 PIN
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Chap3. Timer Interrupt & Optimize
Timer Mode - Mode 3
osc
 12
Timer/Counter 0 Mode 3 : Two 8-bit Counters
C /T  0
TL0
(8BITS)
T0 PIN
TF0
INTERRUPT
C / T  1 CONTROL
TR0
GATE
1/12 fOSC
TH0
(8BITS)
INT 0 PIN
TR1
TF1
INTERRUPT
CONTROL
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Chap3. Timer Interrupt & Optimize
Vector Table (Single Board Case)
EXTERNAL PROGRAM
MEMORY (ROM)
In Our Single - Board Case,
Actual interrupt service routine
have to be exist in the data memory area
(RAM address range: 8000H ~ 9FFFH)
0023
001B
LJMP 80F9H
TF1
0013
LJMP 80F6H
IE1
LJMP 80F3H
TF0
LJMP 80F0H
IE0
000B
0003
0000
INTERRUPT VECTOR TABLE
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