Transcript Synchronisation Primitives

Operating Systems: Segments
Segmentation
Hardware Support
• single user program system:
– wish somehow to relocate address 0 to
after operating system in memory
address 0
for op. sys.
operating
system
address 0
for user prog.
– can then compile and run program as if
from address 0
user
program
• automatic hardware relocation:
– a Relocation Base Register (RBR)
– contents added in to every address before use
» set to 0 when running operating system
» set to address after operating system when
running user program
– program generates virtual addresses
– become physical addresses after adding in the RBR contents
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Operating Systems: Segments
RBR
100000
memory
CPU
virtual address
2345
+
physical
address
102345
– used on the English Electric KDF9
» first ever mainframe in the University of Edinburgh - 1968
» operating system very small and simple – called the Director
» RBR cleared when system call to Director and restored when returning to user
» 48-bit words, zero-addressing for pushdown/popup evaluation stack
– also used on the DEC System-10
» 36-bit words
» first mainframe in Dept. of Computer Science - 1973
» used for Computer Aided Design
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Operating Systems: Segments
• multiprogramming system:
Op. Sys.
Partition 1
Partition 2
Partition 3
– each program must be prevented from accessing another program’s area
• a Limit Register in addition to RBR:
– all virtual addresses must be less than a limit – the partition size
Limit
RBR
memory
CPU
virtual address
yes
<
+
no
– an exception generated into the operating system when limit violated
– each program has its own base and limit values
– limit value is a virtual limit
» hence limit check and base address addition can operate concurrently
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Operating Systems: Segments
• Multiple base and limit registers
– separate pairs for each module e.g. code, data:
code:
RBRcode
LRcode
data:
RBRdata
LRdata
LRcode
LRdata
code
data
RBRcode
RBRcode
– in effect Segment Registers
– CPU knows whether code or data access requested
» hence can relocate using the correct base and limit pair
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Operating Systems: Segments
• Example : Intel 8086 (and Pentium real-address mode)
– a 16-bit machine with 16-bit registers :
7
AX
0 7
AH
15
0
AL
multiply, divide & I/O
DX
DH
DL
CX
CH
CL
BX
BH
BL
loop, shift, repeat & count
0
CS
code segment selector
DS
data segment selector
SS
stack segment selector
ES
extra segment selector
base registers
BP
15
SI
0
F
flags
IP
instruction pointer
index registers
DI
SP
MSW
stack pointer
machine status word
– appropriate segment registers are selected implicitly
» executing code addresses imply code segment register
» stack operations imply stack segment register
» others depend on the registers used in the instruction:
Register
SP
BP
BX
SI
DI
BP+SI/DI
BX+SI/DI
Implied Segment
SS
SS
DS
DS
DS
SS
SS
ES for string operations
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Operating Systems: Segments
» implicit segment register selection can be overridden with an instruction prefix
» new values can be loaded into segment registers at any time
– segments are all 64Kb in length
– physical address calculation:
» CPU addresses generated are 16-bits – regarded as within-segment offset
» segment register value shifted left 4 and added to within-segment offset:
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base
+
offset
=
0 0 0 0
0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0
base
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
linear address
64K segment
– no variable size segments and no limit checking
– segments can overlap in memory
– no differential read/write/execute protection
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Operating Systems: Segments
• Segment Tables
– an indexed array of base & limit pairs:
base
limit
0
1
2
3
virtual address
segment number
within-segment offset
– virtual address partitioned into two parts
» position of partition defines maximum number of segments and their size
– other information also present in each index entry
» presence bit – whether this segment exists and has a valid base and limit
» protection bits – to allow read/write/execute etc. for this segment
» cacheable bit – to allow data in this segment to be cached or not
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Operating Systems: Segments
• Example – 1Mb segments :
0x000000
main program
0x000000
main program
0x100000
0x0A0000
library
data
0 0x000000
1 0x1C0000
0x200000
2
0x0A0000
0x080000
-
-
3 0x0A0000
4 0x300000
0x300000
0x0C0000
0x1C0000
library
0x100000
data
.
.
.
.
0x400000
stack
.
.
.
.
0x300000
stack
physical address space
virtual address space
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Operating Systems: Segments
• Shared segments:
Process 1
0x000000
main program 1
process 1 segment table
0 0x000000
1 0x1C0000
-
0x100000
shared library
0x0A0000
0x080000
.
.
.
.
0x000000
main program 1
0x0C0000
main program 2
process 1 virtual address space
0x1C0000
Process 2
0x000000
main program 2
process 2 segment table
0 0x0C0000
1
-
0x0B0000
2 0x1C0000
0x080000
shared library
-
0x100000
0x200000
shared library
.
.
.
.
physical address space
process 2 virtual address space
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Operating Systems: Segments
• Example : the ARM processor MMU :
– 12-bit section (segment) number, 20-bit offset
– Translation Table Base is a loadable processor register
» new value loaded whenever running process switched
– translation table (segment table) contains descriptors for sections
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Operating Systems: Segments
– level-one descriptor formats :
» AP : access permission bits, read/write, no access etc.
- together with other processor register bits R and S
» Domain : level of access control, client/manager etc.
» C : cacheable bit
» B : bufferable bit – write-through write buffer enable bit
– paging also possible
» two page sizes available, 4Kb and 1Mb blocks
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Operating Systems: Segments
– the full translation process for sections :
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Operating Systems: Segments
• Example : Intel Pentium protected mode :
– 32-bit registers with 16 and 8 bit versions available for backwards compatibility
31
15
7
0
15
0
EAX
AH
AL
AX
CS
code segment selector
EDX
DH
DL
DX
DS
data segment selector
ECX
CH
CL
CX
SS
stack segment selector
EBX
BH
BL
BX
ES
EBP
BP
FS
ESI
SI
GS
EDI
DI
ESP
SP
extra segment selectors
31
status and control registers
0
EFLAGS
EIP
– implicit segment register selection as on 8086
– running program must ensure segment registers loaded with correct selectors
» a selector is an index into a Descriptor Table
» a descriptor table acts as a segment table but many other types of
descriptor also exist:
- e.g. call, interrupt, trap and task gates
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Operating Systems: Segments
– selector structure :
15
3
index
2
TI
1
0
RPL
» TI : table indicator, 0 = Global Descriptor Table, 1 = Local Descriptor Table
» RPL : Requestor Privilege Level, 00 = most privileged, 11 = least privileged
Global Descriptor Table Base Register
base address
limit
Global Descriptor Table
Local Descriptor Table Base Register
base address
limit
Local Descriptor Table
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Operating Systems: Segments
– two descriptor tables :
» one for kernel segments and gates
- same table used all the time
- each process has its own local descriptor table
- saves reloading base register each time kernel entered
» one for each process segments and gates
- local descriptor table base register changed as running process switched
– selector index (13 bits) + TI bit + within-segment offset (32 bits)
» effectively give a 46-bit virtual address :
15
3
31
selector
0
offset
segment descriptor
descriptor table
base
address
31
+
0
linear address
36-bit linear address also
possible on Pentium II up
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Operating Systems: Segments
– descriptor table segment entry :
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base (31:24)
G D
seg lim P DPL S
(19:16)
base address (15:0)
type
base (23:16)
segment limit (15:0)
» base : segment base address
» G : granularity :
- 0 = segment limit expressed in bytes, from 1 byte to 1Mb
- 1 = segment limit expressed in 4Kb units, from 4Kb to 4Gb
» D : default operation size, 0 = 16-bit, 1 = 32-bit
- for backwards compatibility
» P : presence bit
» DPL : descriptor privilege level
» S : system/application descriptor type
» type : segment type
- for access control
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Operating Systems: Segments
– A bit : set when selector has been loaded into a segment register
– expand-down for stacks etc.
» the limit check reversed
– conforming associated with changing privilege levels in new segments
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Operating Systems: Segments
– when a program loads a selector into a segment register :
» hardware uses selector value to index into appropriate descriptor table and
loads base and limit values into invisible part of the segment register:
visible part
CS
selector
invisible part
base address, limit etc.
DS
SS
ES
FS
GS
– access permission to segment validated at time of loading segment register
» never needs to be done again whilst that segment is in use
- much more efficient
– checks involve:
» processes current privilege level (CPL)
» descriptor privilege level (DPL)
» requestor privilege level (RPL)
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Operating Systems: Segments
– CPL is held in the two lowest bits of the code segment (CS) register
» normally is the same as the privilege level of the current code segment
- except for conforming segments called from a less privileged level
» changes when control passes to a code segment with a different privilege level
– instructions may only load a segment register if CPL  DPL
» i.e. process has a greater or equal level of privilege as the segment
» Rings of Protection
higher
privilege
– RPL is in the segment selector
» represents the privilege level of the
0
procedure which created the selector
1
» when RPL  CPL, this value overrides
2
lower
the CPL for accesses using that selector
3
privilege
» used to guard against a security violation
in which a less privileged program requests
a more privileged program to access protected data
» data can be given a lower privilege RPL to protect it, even though the program
doing the accessing might otherwise have sufficient privilege to do so
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Operating Systems: Segments
• Multitasking on Pentiums
– Task State Segment (TSS)
» for each process, holds volatile
context (PCB) for that process
» a segment with a descriptor in
the Global Descriptor Table
– Task Register (TR)
» identifies the current TSS
– Interrupt Descriptor Table Register
(IDTR)
» a segment register for the segment
which holds the Interrupt Descriptor
Table
» when an interrupt occurs, this table
is used as an interrupt vector
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