Transcript Slide 1
Status on development of a White Rabbit Core P.P.M. Jansweijer, H.Z. Peek P. Jansweijer Nikhef Amsterdam ElectronicsTechnology December 10, 2010 WR Developer Meeting 1 Spartan-6 (SP605) P. Jansweijer Nikhef Amsterdam ElectronicsTechnology December 10, 2010 WR Developer Meeting 2 Master/Slave test setup block diagram Bidirectional Loopback the recovered clock @ 1.25 Gbps conform standard IEEE 802.3 (1000BASE-X, Gigabit Ethernet) Master Slave TxUsrClk RxUsrClk Tx Rx Start SFP Stop Rx P. Jansweijer Nikhef Amsterdam ElectronicsTechnology RxUsrClk SFP Slave BitSlide Tx Master BitSlide TxUsrClk Master + Slave BitSlide For details please see Technical Report “ETR2010-01”: http://www.nikhef.nl/pub/services/biblio/technicalreports/ETR2010-01.pdf December 10, 2010 WR Developer Meeting 3 Spartan-6 Test setup 10 Km fiber Using two SP605 Evaluation Platforms (XC6SLX45T‐3FGG484CES) Stop Stop Clock Loopback (DPLL) DAC Start Master P. Jansweijer Nikhef Amsterdam ElectronicsTechnology VCXO Slave December 10, 2010 WR Developer Meeting 4 Resynchronization in action 011101011000001010110111010110000010101101110101 3 10 RxRecClk BitSlide(4:0) 0 P. Jansweijer Nikhef Amsterdam ElectronicsTechnology Unit Interval (UI) 0001 = 3 0000 0011 1 0 Start/Stop delay Algorithm: Propagation Delay = “Start-Stop” Delay + “LED Value” * UI December 10, 2010 WR Developer Meeting 5 FPGA SerDes remarks The Receiver Deserializer should provide a means to (manually control) “Bit Slip”. Tested in: Family SerDes Name Bit Slip Test Xilinx Virtex-5 GTX RxSlide Okay Xilinx Virtex-5 GTP RxSlide +/- 1 UI Remark Xilinx ug196 Table E-2 P. Jansweijer Nikhef Amsterdam ElectronicsTechnology Xilinx Spartan-6 Rx_BitSlip RxSlide Okay Xilinx Virtex-6 ? ? ? Altera Stratix-IV-GX GXB Rx_BitSlip Okay Lattice SC/M FlexiPCS x Fail December 10, 2010 WR Developer Meeting 6 SP605 FMC connector debug LEDs Master Slave PLL_LockDetect RxInSync TxRxLocked PLL_LockDetect RxInSync 4 P. Jansweijer Nikhef Amsterdam ElectronicsTechnology Master + Slave BitSlide (4..0) 3 0 0 December 10, 2010 Slave BitSlide (3..0) WR Developer Meeting 7 XC6SLX45T GTP Clock configuration issue RefClk RefClk GTPA1_DUAL_X0Y0 GTPA1_DUAL_X1Y0 RefClk RefClk GTPA1_DUAL_X0Y0 GTPA1_DUAL_X1Y0 Prevents fibre (SFP) implemenation + SMA Clock Input (needed for VCXO) on SP605 P. Jansweijer Nikhef Amsterdam ElectronicsTechnology - Place & Route software bug? Silicon bug? Engineering sample/production device? => Xilinx Web Case 855178 December 10, 2010 WR Developer Meeting 8 Spartan-6 Test setup via SMA Stop Start X4:X4 a few hundred ppm of target frequency C324/C325 Master SMA Cables Clock Loopback (DPLL) Using two SP605 Evaluation Platforms DAC Slave P. Jansweijer Nikhef Amsterdam ElectronicsTechnology VCXO December 10, 2010 WR Developer Meeting 9 WR Core block diagram (Slave) “The Ugly Switch Endpoint Diagram” RX_ER RX_DV Receive Engine Rx Fifo VCXO GTX_CLK Flow Control SFD Detect PHY (GTP) gRS 802.3bf RX_CLK SFP Transmit Engine TXD<7:0> TX_EN TX_ER SYSTIM P. Jansweijer Nikhef Amsterdam ElectronicsTechnology BitSlide t1, t4 Client Interface GMII RXD<7:0> Address Filter Tx Fifo Management Configuration Client (may be software) SFD Detect MAC 72 5 Time Stamp RXSTMP H/L (t2) TXSTMP H/L (t3) t2, t3 RXSATR H/L SourceID/SequenceID December 10, 2010 WR Developer Meeting 10 Interesting literature INTEL 82580 datasheet ◦ Quad Gigabit Ethernet LAN + PTP Controller Chapter 7.9: “Time SYNC” IEEE 802.1AS ◦ defines protocol and procedures for the transport of timing over Bridged and Virtual Bridged LAN P. Jansweijer Nikhef Amsterdam ElectronicsTechnology IEEE802.3bf ◦ defines the Time Synchronization Service Interface (TSSI) ◦ gRS: generic Reconciliation Sublayer December 10, 2010 WR Developer Meeting 11 OpenCores ZPU (embedded processor) P. Jansweijer Nikhef Amsterdam ElectronicsTechnology December 10, 2010 WR Developer Meeting 12 ZPU Hello World CP2103 RS232 ZPU CORE USB Memory 64 KB Wishbone Interconnect Open Cores UART 16550 P. Jansweijer Nikhef Amsterdam ElectronicsTechnology December 10, 2010 WR Developer Meeting 13 ZPU results Very small system ◦ ◦ 784 Flip-Flops (~ 6% LUT/CLB of XC6SLX45T) 64KB (= 27% RAMB16BWERs of XC6SLX45T) Open Cores => Several ZPU cores (but not the one we need): P. Jansweijer Nikhef Amsterdam ElectronicsTechnology ◦ “ZPU_Core” Preffered type “ZPU_Core _small” uses Dual Port Memory “Zealot” = ZPU_Core + UART + Timer “ZY2000” = ZPU_Core + Whisbone (but using non IEEE VHDL libraries) => Took ZPU_Core and looked at ZY2000 to create ZPU_Core + Wishbone December 10, 2010 WR Developer Meeting 14 ZPU results-2 Tools operational: ◦ Hardware ◦ Software Cygwin, GNU toolchain Last Open Cores update = September 2009 ◦ But ZPU mailing list is alive and kicking Future study: Resetting the core sometimes creates a hang. P. Jansweijer Nikhef Amsterdam ElectronicsTechnology Simulation (ModelSim scripts to fill Memory with “elf”) ISE, Memory Core Generator, BMM files, Data2Mem ◦ Has got to do with software (over)writing the start-up vector at some point... December 10, 2010 WR Developer Meeting 15 Some more general remarks: WR Specification! ◦ ◦ How do we deal with delay asymmetry? ◦ P. Jansweijer Nikhef Amsterdam ElectronicsTechnology Link delay model John Eidson remarks Calibration? Thank you December 10, 2010 WR Developer Meeting 16