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Verilog Hardware Description
Language
• Sections in Chapter 3-9
• Digital Design, 4th Edition
• M. Morris Mano and micchael D.
Ciletti
1
Introduction
• HDL stands for Hardware Description
Language
• Used to describe digital system in textual
form
• Oriented to the structure and behaviour of
digital systems
• Verilog HDL programs can be read by
both human and computer
• Tow main applications of HDL
— Logic Simulation
— Logic Synthesis
2
Logic Simulation
• Representation of structure and behaviour
of digital systems using computer
• The simulator interrupts the HDL
description and produce readable output
(table, timing diagram, ..)
• This process help in predicting how digital
system will behave before fabrication
• The stimulus that test the design is called
Test Bench (written in HDL)
• To simulate a digital system:— Write the HDL description for the system
— Verify using Test Bench
3
Logic Synthesis
• Driving a list of components and its
interconnection (net list) from a module
described in HDL
• Used to fabricate integrated circuits or
printed circuit board
• Same as conventional high level
language, the difference is it produce a
database with instruction how to fabricate
the physical piece of the digital system
Source Code
Conventional Lang
Compilation
Object Code
4
Logic Synthesis (continue)
Source Code
Logic Synthesis
Compilation
Database with
Instruction to
Fabricate system
5
Historical Background
• Two main standard supported by IEEE
— VHDL
— Verilog HDL
VHDL
— Developed by Department of defense
— Like Ada Programming language
Verilog HDL
— By Cadence Data System (late1990)
— Easier than VHDL, like C language
6
Simple Verilog HDL Example #1
Write a verilog HDL description for the
following circuit using gate level
module or_nand_1 (enable, x1, x2, x3, x4, y);
input enable, x1, x2, x3, x4;
output y;
wire w1, w2, w3;
or (w1, x1, x2);
or (w2, x3, x4);
or (w3, x3, x4); // redundant
nand (y, w1, w2, w3, enable);
endmodule
7
Simple Verilog HDL Example #2
Write a verilog HDL description for the
following circuit using Data flow
module or_nand_2 (enable, x1, x2, x3, x4, y);
input enable, x1, x2, x3, x4;
output y;
assign y = !(enable & (x1 | x2) & (x3 | x4))
endmodule
8
Simple Verilog HDL Example #3
Write a verilog HDL description for the
following circuit using behavioral
module or_nand_3 (enable, x1, x2, x3, x4, y);
input enable, x1, x2, x3, x4;
output y;
reg y;
always @ (enable or x1 or
x2 or x3 or x4)
if (enable)
y = !((x1 | x2) & (x3 | x4));
else
y = 1; // operand is a constant.
9
endmodule
Structure of Verilog HDL
description
• Module is the building block
• Every module declared by module and
terminated by endmodule
• Module look like
module module_name ( port_list );
port declarations;// input, output
variable declaration; // wire, reg
…
description of behavior // instantiation,
// statements
endmodule
10
Verilog basic concepts
Keyword in Verilog
• About 100 keyword
• Must be in lowercase (case sensitive)
• Examples of keywords are:module, input, reg, and, for,
else, not, if, case, always,
nand, wire, endmodule, ….
Comments in Verilog
• // single line
• /* multiple lines
*/
11
Verilog basic concepts (continue)
Identifiers in verilog
• May begin with alphabetic or underscore
• May contain:— digits 0 – 9, $, 0r _
Logic values
• Verilog has 4 logic values
— logic 0, logic 1
—z or Z high impedance
—x or X unknown
12
Verilog basic concepts (continue)
Number specification
• Two types of number specification:—Sized and unsized
Sized numbers
• General form:- size ‘base value
— Size is written in decimal, specify # of bits
— Base, format is:–d
–b
–o
–h
or
or
or
or
D, for decimal, example 5 ‘d 132 (5-bits)
B, for binary, example 4 ‘b 1011 (4-bits)
O, for octal,
example 5 ‘o 132 (5-bits)
H, for hex,
example 12 ‘h a45c (12-bits)
13
Verilog basic concepts (continue)
• The size is optional, default is 32-bits
• The base is optional, default is decimal
Unsized numbers
• Without base format
— example ‘h 3b (32-bits hex)
— 45678 ( 32-bits decimal by default )
X and Z values
• Denoted by x (unknown) and z (high imp)
—8’h5x, 8-bits hex number; 4 LSB are unknown
14
Verilog basic concepts (continue)
Arithmetic operators
• Two types: binary and unary (sign; + & -)
• +, -, * , /, and % (Modulus)
Example
if A = 4 ‘b0011 and B = 4’b 0100, then
—
—
—
—
A + B = 4’b0111
B - A = 4’b0001
3 + 7 = 10 (decimal)
5% 2 = 1 (decimal)
• - 4 Negative 4 (unary)
15
Verilog basic concepts (continue)
Bitwise Operators
• ~ (inverting), & (AND), | (OR), ^ (XOR),
^~ or ~^ (XNOR)
• Performed a bit-by-bit operation on two
operands (corresponding bits )
• If one operand is shorter than the other, it
will be extended with 0’s to match longer
Example
if A = 4 ‘b0011 and B = 4’b 0101, then
— Y = ~A;
Y = 4’b 1100
— X = A & B; X = 4’b 0001
— Z = A ^ B; Z = 4’b 0110
16
Verilog basic concepts (continue)
Reduction Operator
• Are:- & (AND),| (OR), ^ (XOR), ^~ or ~^
(XNOR) but on one operand, yield to 1-bit
• Work bit by bit from right to left
Example
if A = 4 ‘b0011, then
— Y = &A; Y=’b 0, equivalent to (0 & 0 & 1 & 1)
Logical Operators
• ! (NOT (unary)), && (AND), || (OR),
17
Verilog basic concepts (continue)
• Evaluate to 1-bit, false (0), true(1), or x
• Non zero is logic 1, and zero is logic 0
• Operands can be :- values or expression
Example
if A = 4 and B = 0, then
— Y = A && B;
— X = A || B;
Y=0
X=1
Note Do not confuse between Bitwise,
reduction and logical operators
18
Verilog basic concepts (continue)
Relational operators
• > (grater), >=(grater or equal), <(less
than),<=(less or equal)
• Evaluate to true (1) or false (0)
Example
if A = 4, B = -2, C= 3’b001, and D=3’b1xz
then
— Y = A > B;
Y=1
— X = C <= D ; X = x (any x or z bits in the
operand, the result is x)
19
Verilog basic concepts (continue)
Equality Operators
• == (equal to),!= (not equal to),===
(case equal to), !== (case not equal to)
• == and != yield to 1, 0, or x (if operand
has x or z bits)
• === and !== yield to 1 or 0
— Compare both operand bit by bit including x
and z, result is 1 if complete match
Example
if A = 3’b0xz, and B=3’b1xz, then
— Y = A == B;
Y=x
— X = A === B ;
X=0
20
Verilog basic concepts (continue)
Logical shift operators
• << (shift left) and >> (shift right)
Example
if x= 5’b01110, then
— Y = x >> 2,
— Y = x << 1,
y = 5’b00011
y = 5’b11100
Concatenation Operator
• {m , n} means concatenate m to n
• Operands must sized
21
Verilog basic concepts (continue)
Example
if A = 4 ‘b0011 and B = 4’b 0100, then
— Y = {A,B}, Y = 8’b00110100
— Y = {010,B}, Y = 7’b0100100
Replication operator
• Replicate concatenation a number of time
• { 3{m}}, replicate m operand 3 times
Example
— Y = {3{01}}, Y = 010101
— Y = {3{01}, 2{10}}, Y = 0101011010
22
Verilog basic concepts (continue)
Conditional Operator
• ?: , takes three operands
• Syntax Cond_exp ? T_exp : F_exp,
— Evaluate Cond_exp, if:– True select T_exp
– False select F_exp
Example
read a value for mark, then
— Grade =mark >= 60 ?pass : fail
– if mark = 70 (say), then Grade = pass
23
HDL For Combinational Circuits
• A module is described in any one (or
combination) of the following techniques:Gate-Level modeling:- Instantiation of
primitive gates and user-defined module
Dataflow modeling:- Using continuous
assignment statements with the keyword
assign
Behavioral modeling:- Using procedural
statements with the keyword always
24
Gate-Level Modeling
• Describe the circuit by specifying gates
and their interconnection
• Provide textual description of a schematic
• Verilog recognize 12 basic gates
— 4 are of 3-state type (see fig 4-31)
— Other 8 gates are :- and, or, nand, nor,
xnor, xor, not, buf
• When the gates are simulated, the system
assign a 4-valued logic set to each gate
— 0, 1, X, when I/P or O/P is ambiguous (not 0
or 1 ), z, occurs in O/P of a 3-starte gate or if
the wire is unintentionally left unconnected
25
Gate-Level Modeling (continue)
• O/P of a gate is evaluated as soon as one
of the I/P’s changed
• Table 4.9 shows truth table for:- and, or,
xor, not gates
• and & or truth tables are shown below
and 0 1 x z
0
1
x
z
0
0
0
0
0
1
x
x
00
xx
xx
xx
or 0 1 x z
0
1
x
z
0
1
x
x
1
1
1
1
xx
11
xx
xx
26
Gate-Level Modeling (continue)
• When a primitive gate is incorporated in a
module, we say it is instantiated in the
module
Instances
• Instantiation is the process of creating
actual objects from module template
• When module is invoked, HDL creates
unique objects (copies) called instance
27
Gate-Level Modeling (continue)
module muxor_4_1 (A,B, c0, c1, c2, c3, y);
input A,B, c0, c1,
c2, c3;
output Y;
wire a_inv,b_inv,
y0, y1, y2, y3;
not (a_inv, A);
not (b_inv, B);
and (y0,c0,a_inv,b_inv);
and (y1,c1,a_inv,B);
and (y2,c2,A,b_inv);
28
Gate-Level Modeling (continue)
and (y3,c3,A,B);
or (Y, y0,y1,y2,y3);
endmodule
Gate instantiation
• Without instance name
— and (y3,c3,A,B);
• With instance name
— and G1 (y3,c3,A,B);
• Both are legal in Verilog HDL
29
Gate-Level Modeling (continue)
Gate delay
• In real circuits, logic gate have delay
• Gate delay is specified by # (value)
Example
module half_adder_gates(x,y,sum,carry);
input x, y;
output sum, carry;
and #(10) (carry, x, y);//10 unit delay
xor u_sum #(5) (sum, x, y);//5 unit ,,
endmodule
30
User-Define Primitive (UDP)
• Logic gates (and, or, …) used in HDL are
define by the system are referred to as
system primitive (built in primitive)
• User can create additional primitives by
defining them in a tabular form (Truth
table), referred to as UDP
• UDP is declared by the keyword primitive
• UDP take only scalar I/P terminals (1 bit)
• UDP can have only 1 scalar O/P terminal
• In sequential UDP, O/P must be declared
as reg (since sequential UDP store state)
31
User-Define Primitive (continue)
Example (Design a half adder using UDP)
primitive HA (s, A, B);// O/P terminal must
output s;
// always appear first
input A, B;
// in the terminal list
table
0 0 : 0; // Any # of I/P’s, only one O/P
0 1 : 1; // I/P’s & O/P are separated by :
1 0 : 1; // truth table enclosed by table &
1 1 : 0; // endtable,
endtable
endprimitive
32
User-Define Primitive (continue)
• Input entries of the table must be in the same
order as the input terminal list (… )
• UDP can’t be defined inside module, they can
only be instantiated exactly as gates
Example (Design a and gate using UDP)
primitive upd_and (OP, x, y);
output OP; input x, y;
table
0 0 : 0;
0 1 : 0;
1 0 : 0;
1 1 : 1;
endtable
endprimitive
33
Instantiating UDP primitive
Example
Design a half adder using udp_and primitive
module half_adder_gates(x,y,sum,carry);
input x, y;
output sum, carry;
udp_and (carry, x, y);/*instantiated
exactly like Verilog gate primitive*/
xor u_sum #(5) (sum, x, y);//5 unit ,,
endmodule
34
Dataflow Modeling
• Gate-level modeling for small circuits
• In complex design, gates # is very large,
more effective to use higher modeling
• Dataflow provide a very powerful way to
implement design (specially complex one)
• Verilog allows a circuit to be design in
terms of data flow between registers
• Dataflow is a popular and sophisticated
approach as a Logic synthesis (creating a
gate-level circuits from dataflow design)
• Dataflow uses a # of operators that acts
on operands to produce the design
35
Dataflow Modeling (continue)
• Verilog provide 30 operators (table 8.1)
—Explained previously
Continuous Assignments
• Most basic statement in dataflow, used to
drive (assign) a value to a net
• A net defines a gate O/P declared by an
output or wire keyword
• A continuous assignment statement starts
with the keyword assign
Syntax is assign net = expression
—Operators; all possible operation (+, &, >, ..)
36
Dataflow Modeling (continue)
Continuous Assignment characteristics
• LHS must always be a net (scalar, vector,
or concatenation), can’t be a register
• RHS operands can be registers or net
• Always active, evaluated as soon as one
of the RHS operand changed
• All continuous assignment statements
execute concurrently (Order of statement
does not impact the design)
• Delay can be introduced
—Example: assign #2 sum = a ^ b;
— “#2” indicates 2 time-units
37
Dataflow Modeling (continue)
Example
Write a Verilog description for a half adder
using Dataflow modeling (Boolean Exp.)
• module half_adder (x,y,sum,carry);
input x, y;
output sum, carry;
assign #5 sum = x ^ y;//logic equation
assign #5 carry = x & y;// logic equation
endmodule
38
Dataflow Modeling (continue)
Example
Write a Verilog description for a full adder
using Dataflow modeling (Arithmetic)
• module Full_adder (x,y,c_in,sum,carry);
input x, y, c_in;
output sum, carry;
assign {carry, sum} = x + y + c_in;
endmodule
• The target output is the concatenation of
carry and sum (2-bits)
• A single statement binary addition
39
Dataflow Modeling (continue)
Example
Write a Verilog description for 8-bit binary
full adder using Dataflow modeling
• module Binary_F_A (x,y,c_in,sum,carry);
input c_in,[7:0]x,y;/* x, y are declared as
vectors (multiple bit widths)*/
output [7:0]sum; output carry;
assign {carry, sum} = x + y+ c_in ;
endmodule
• The target output is 9-bits {1-bit, 8-bit}
40
Dataflow Modeling (continue)
Example
Write HDL description for x = A+BC+B’D
using Dataflow modeling
module Binary_F_A (x, A, B, C, D);
input A, B, C, D;
output x;
assign x = A | B&C | ~B&D;/* Verilog uses
&, |, ^, ~, ~^, ~&, ~| logic operators*/
endmodule
41
Dataflow Modeling (continue)
Example (2-to-4 line decoder, Fig4-19);
module Decoder_DF (A, B, En, D);
input A, B, En;
output [0:3] D;
assign D[0] = ~(~A & ~B & ~En) ,
D[1] = ~(~A & B & ~En),
D[2] = ~(A & ~B & ~En) ,
D[3] = ~(A & B & ~En);
endmodule
• 4 continuous statements, always active,
LHS evaluated as soon as one of the RHS
operand is changed
42
Dataflow Modeling (continue)
Example (Dataflow description of a 4bit magnitude comparator, Fig 4-17);
module mcomp (A, B, ALTB, AGTB, AEQB);
input [3:0] A, B;
output ALTB, AGTB, AEQB;
assign ALTB = (A <B) ; // One of the O/P’s
assign AGTB = (A >B) ; // is logic 1
assign AEQB = (A ==B) ;
endmodule
• Synthesis compiler accept this module as
I/P and provide a netlist equiv. to Fig 4.17 43
Dataflow Modeling (continue)
Example (Dataflow description of a 2-1
line Mux);
module mux2_1 (A, B, sel, out);
input A, B, sel;
output out;
assign out = sel ?A :B ;
//or assign out = (sel & A) | (~sel & B);
endmodule
• The conditional operator is used
— condition ? true_exp : false_exp
44
Behavioral Modeling
• The process of representing the digital
circuits at a functional and algorithm level
• Behavioral Modeling similar to C language
• Behavioral Modeling mostly used for
sequential circuits
Why Behavioral Modeling
• Allow designer to evaluate, trade-off of
various architecture and algorithm
• Choose the optimum to implement
• Verilog is rich in behavioral constructs
that provide designer with great flexibility
45
Behavioral Modeling (continue)
Structured Procedure
• Two structured procedure in Verilog are
initial & always, these are the most basic
statement in behavioral modeling
• All other behavioral statement appear
inside these statement
• always & initial can’t be nested. Each one
represents a separate activity
• Each activity starts at simulation time 0
Target output
• Must be of reg data type (not a wire)
46
Behavioral Modeling (continue)
• reg remains unchanged until a new value
is assign by procedural assignment
initial statement
• All statements inside an initial statement
constitute an initial block
• An initial block start at time 0
• An initial block execute only once
• Multiple blocks execute concurrently
• begin & end must be used to group
multiple behavioral statements
47
Behavioral Modeling (continue)
always statement
• Behavioral descriptions use the keyword
always followed by list of procedural
(behavioral) statement
• The always constitute an always
• An always block start at time 0
• An always block execute continuously
—Control of always (stopping) explained later
• begin & end must be used to group
multiple behavioral statements
48
Examples on initial and always
reg clock; // clock can’t be declared as wire,
initial
// it can’t be used in initial
begin
clock = 0;
# 50 clock = 1;
# 30 clock = 0;
# 20 clock = 1;
end
// example on always
reg Clock;
initial
Clock = 0;
always
#10 Clock = ~ Clock; //forever (clock)
49
Behavioral Modeling (continue)
The if Statement
Syntax:
if (condition)
procedural_statement;
Example
if (enable)
out = a;
Example
if (enable)
begin
out = a;
enable = 1’b0;
end
50
Behavioral Modeling (continue)
The if else Statement
Example:
if (sel == 1)
out = a;
else out = b;
Nested if else if Statement
if (input== 1)
out = a;
else if (input == 2)
out = b;
else if (input == 3)
51
Behavioral Modeling (continue)
out = c;
else if (input == 4)
out = d;
Case Statement
Example 1:
case (X)
2’b00: Y = A
2’b01: Y = A
2’b10: Y = A
2’b11: Y = A
endcase
+ B;
– B;
/ B;
* B;
52
Behavioral Modeling (continue)
Example 2: (case)
case (3’b101 << 2)
3’b100: A = B + C;
4’b0100: A = B – C;
5’b10100: A = B / C; //This statement
// is executed
default: $display (“ error”); // optional
endcase
Case with x and z values
• Casez :- Treats z as don't care
• Casex :- Treats x and z as don't care
Behavioral Modeling (continue)
Loop Statements:—repeat , while, for, and forever
Repeat Loop
repeat (Count)
sum = sum + 5;
While Loop
while (Count < 10) // execute until false
begin
sum = sum + 5;
Count = Count +1;
end
54
Behavioral Modeling (continue)
For Loop
for (Count = 0; Count < 10; Count =
Count + 1)
sum = sum + 5;
Note:- For all loops above, if condition is a x
or z, it is treated as 0
Forever loop
forever #5 clk = ~clk; // execute forever,
// until $finish
55
Behavioral Modeling (continue)
Example ( 4-to-1 line Mux, using if else )
module mux4_1 ( a, sel, y);
a[0]
input [3:0] a;
a[1]
y
input [1:0] sel;
a[2]
output y;
a[3]
reg y; // target output
always @ (sel or a) // no ;
sel[1:0]
if (sel == 0)
y = a[0];
else if (sel == 1) y = a[1];
else if (sel == 2) y = a[2];
else if (sel == 3) y = a[3];
endmodule
56
Behavioral Modeling (continue)
Notes on Example ( 4-to-1 line Mux)
• Y is a target output, must be declared as
reg
• Procedural assignment inside always block
are executed every time there is:— a change in any variable after @
• The or between variables in the always is
not logic, it is language or
• The always block starts at time = 0
• The always w/o @ execute continuously
• $finish can be used to stop execution
57
Behavioral Modeling (continue)
Example ( 4-to-1 line Mux, using case )
module mux4_1 ( a, sel, y);
a[0]
input [3:0] a; input [1:0] sel; a[1]
output y; reg y; // target o/p a[2]
a[3]
always @ (sel or a) // no ;
case (sel ) // or ({sel[1],sel[0]})
0: y = a[0];
sel[1:0]
2’b01: y = a[1]; // binary or decimal
2: y = a[2];
3: y = a[3];
endcase
endmodule
y
58
Behavioral Modeling (continue)
module mux_4bits (y, a, b, c, d, sel);
input [3:0] a, b, c, d;
input [1:0] sel ;
output [3:0] y; reg [3:0] y;
always @ (a or b or c or d or sel)
case (sel)
a[3:0]
2’b00: y = a;
b[3:0]
y[3:0]
1: y = b;
c[3:0]
d[3:0]
2’b10: y = c;
3: y = d;
default: y = 4'bx;
sel[1:0]
endcase
59
endmodule
Behavioral Modeling (continue)
Example ( 3-to-8 Decoder, using case)
module Decoder3_8 (in, enable, out);
input [2:0] in; input enable ;
output [7:0] out; reg [7:0] out;
always @ (in or enable)
begin
out = 0;
if (enable)
begin
case (in)
3'h0 : out = 8'h01;
3'h1 : out = 8‘h02;
60
Behavioral Modeling (continue)
3'h2 : out
3'h3 : out
3'h4 : out
3'h5 : out
3'h6 : out
3'h7 : out
endcase
end
end
endmodule
=
=
=
=
=
=
8‘h04;
8‘h08;
8‘h10;
8‘h20;
8‘h30;
8‘h40;
61
Test Bench
• Verilog HDL program used for applying a
stimulus to an HDL module for testing
• Normally takes time to develop, care must
be taken to ensure complete circuit test
• The always & initial statements are used
to provide stimulus to the circuits
• The always & initial starts at time 0
• The initial execute only once, while always
repeatedly (depends on the event control)
• Specifying time delay is a good habit
• Following the stimulus module form
62
Test Bench (continue)
Stimulus module form
module test_name;//nothing goes in / out
//declare local reg // related to I/P of tested
// module
and wire // related to O/P of tested
// module
//instantiate the module under test
//generate stimulus using always & initial
//Display the output (text or graphics (or
both))
endmodule
63
Test Bench (continue)
Stimulus and tested
module interaction
• No passing values
to or out of the
stimulus
• The tested module
is instantiated into
the stimulus
• Stimulus generate
inputs to design
module
• Also see Fig 4-33
64
Examples on Test bench
module stimulus1;
reg x, y, a, b, m; // inputs
initial
m = 1’b0 // at time = 0, m is set to 0
initial
begin
x= 1; y=1;//at time= 0, x&y are set to 0
# 10 b = 0;// at time = 10, b is set to 0
# 20 a = 1; // at time = 30, a is set to 1
end
initial
# 50 $finish;
endmodule
65
Examples on Test bench (continue)
module stim2;
reg [0:3] D; // 4-bits
initial
begin
D=4’b 0000;//at time= 0, D is initialized
repeat (15); // looping
# 10 D = D + 1; // add 1 to D every 10
// time unit
end
endmodule
66
Sequential and Parallel Blocks
Sequential Blocks
• begin & end are used to group statements
• Statements in the block are executed in
the order they are specified
• Delay is relative to the simulation time of
the previous statement
Parallel Blocks
• fork & join are used to group statements
• Statements are executed concurrently
• Delay is relative to the block time ( zero ) 67
Example on fork and join
module parallel;
reg x, y, a, b, m; // inputs
initial
# 15 m = 1’b0 // at time = 15, m is set to 0
initial
fork
# 5 x = 1; // at time= 5, x is set to 1
# 3 y = 0; // at time= 3, y is set to 0
# 10 b = 0; // at time = 10, b is set to 0
# 20 a = 1; // at time = 20, a is set to 1
join
initial
# 50 $finish; endmodule
68
Blocking and Nonblocking ( = )
• There are two procedural assignments
—Blocking and Nonblocking
—Blocking use =, Nonblocking use <= operators
—Nonblocking assignments execute concurrently
Example
Suppose A = 5, B = 7, Then
B=A
B <= A
C=B+1
C <= B + 1
Here C = 6
Here C = 8
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Control Event
Level Triggered Event Control
@ (A or B) //Level trigger
Out = A & B;
• Edge Triggered Event Control
@ (posedge CLK / negedge CLK)
Q= D // DFF
—Transfer of data (D to Q) is synchronized by
the Edge transition
of CLK
70
System tasks
Display tasks
1. $display (one-time display)
— Displays the entire list at the time when
statement is encountered with end of line
Example
$display (“ A =%d %b %h”, A, n, m);
— Display A= value of A in decimal
— Display value of n in binary
— Display value of m in hexadecimal
2. $write:-same as $display
— But w/o end of line
71
System tasks (continue)
3. $monitor
— Displays the entire list Whenever there is a change in
any argument value during simulation run
Example
module monitor_display;
reg clk, rst, en, data; // inputs
initial
begin
$monitor (“time =%g clock=%b reset=%b enable
=%b data =%b”, $time, clk, rst, en, data)
# 1 clk = 0;
# 10 rst = 1;
# 5 en = 0; # 3 data = 1;
end
72
endmodule
System tasks (continue)
Output looks like
time = 0 clock =x reset =x enable =x data =x
time = 1 clock =0 reset =x enable =x data =x
time = 11 clock =0 reset =1 enable =x data =x
time = 16 clock =0 reset =1 enable =0 data =x
time = 19 clock =0 reset =1 enable =0 data =1
Example
repeat the last example using fork and join
module monitor_fort_join;
reg clk, rst, en, data; // inputs
7373
System tasks (continue)
initial
fork
$monitor (“time =%g clock=%b reset=%b enable
=%b data =%b”, $time, clk, rst, en, data)
# 1 clk =0; #10 rst =1; # 5 en =0; #3 data =1;
join
endmodule
Output looks like
time = 0 clock =x reset =x enable =x data =x
time = 1 clock =0 reset =x enable =x data =x
time = 3 clock =0 reset =x enable =x data =1
time = 5 clock =0 reset =x enable =0 data =1
time = 10 clock =0 reset =1 enable =0 data =1
74
System tasks (continue)
Simulation Control Task
• $finish : makes the simulator to exit
example # 1000 $finish
— terminate the simulation after 1000 time unit
• $stop : suspends the simulation
Time
• $time: gives the simulation time
75
Test bench for AND gate X = 0 Y = 0 F = 0
module and_T();
X=1Y=0F=0
X=1Y=1F=1
reg X, Y;
X=0Y=1F=0
wire F;
and U1(F,X, Y);//instantiation of the module AND
//instance name is required (must)
// Test bench Code 1
initial begin
$monitor ("X = %b Y = %b F = %b", X, Y, A);
X = 0; Y = 0;
#1 X = 1;
#1 Y = 1; #1 X = 0; #1 $finish; end
76
endmodule
Test Bench (example)
Test bench with stimulus for the mux_2_1
module test_mux_2_1;
wire t_out;
reg t_A, t_B, t_select;
parameter stop_watch = 100;
mux_2_1 MX1 (t_out, t_A, t_B, t_select)//
instantiation of the circuit to be tested
initial # stop_watch $finish ;
initial begin
$monitor (“select = %b A = %b B = %b out = %b
time = %g ", t_select , t_A, t_B, t_out , $time);
t_select=1; t_A=0; t_B=1;
77
#10 t_A=1; t_B=0;
Test Bench (examples)
#10 t_select=0;
#10 t_A=1; t_B=1; end
endmodule
// 2 to 1 mux description
module mux_2_1 (output out, input A, B, select);
assign out =(select)?A: B;
endmodule
The output look like
select
select
select
select
=
=
=
=
1
1
0
0
A
A
A
A
=
=
=
=
0
1
1
0
B
B
B
B
=
=
=
=
1
0
0
1
out
out
out
out
=
=
=
=
0
1
0
1
time
time
time
time
=
=
=
=
0
10
20
30
78
Flip-Flops and latches HDL Description
D Latch HDL Description
module D_latch (output reg Q, input D, enable);
always @ (enable, D) // Verilog 2001, 2005
if (enable)
Q <= D;// using of = is ok
endmodule
D flip-flop with asynchronous reset
module D_latch (output reg Q, input D, clk, rst);
always @ (posedge clk, negedge rst)
if (rst==0)
Q <= 1’b0;
else Q <= D;
endmodule
79
Flip-Flops and latches HDL Description
(continue)
Notes
• Transfer of D into Q is synchronized with positive
edge of clk
• Hardware always has a reset signal. It is strongly
recommended to include a reset input in modules
• After the @ in the always any number of edge
event, for hardware one of the event must be a
clock event
80
T flip-flop from D flip-flop and gates
module TFF (output Q, input T, clk, rst);
wire DT;
assign DT = Q^T
// DT = Q XOR T
D_latch TF1 (Q, DT, clk, rst); // instantiate the D
// flip-flop
endmodule
module JkFF (output Q, input J, K, clk, rst);
wire DJK;
assign DJK = (J&~Q)|(~K&Q) // DJK = JQ’ +K’Q
D_latch JK1 (Q, DJK, clk, rst);// instantiate the D
// flip-flop
endmodule
81
• s
82