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IDEAL-IST Workshop
Christos P. Sotiriou,
Institute of Computer Science,
FORTH.
[email protected]
2/6/2003
IDEAL-IST Workshop, Christos P.
Sotiriou, ICS-FORTH
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FORTH
• FORTH - Foundation for Research and Technology - Hellas.
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Established in 1983.
Internationally recognised R&D centre.
7 institutes, 280 Researchers, 735 Personnel (1999).
~30,000,000E of annual budget.
performs high-quality basic research.
Development of innovative technologies.
founder of many start-ups, FORTHnet is one of them.
contributes to the development of Science&Technology parks.
collaborates with the University of Crete and other Universities.
IDEAL-IST Workshop, Christos P.
Sotiriou, ICS-FORTH
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VLSI Group Activities
• Packet Switch Architectures (M. Katevenis)
– commodity switches.
– multi-gigabit switching fabrics with backpressure.
• Scalable Computing Infrastructures (A. Bilas)
– system area networks (SAN).
– single-system-image clusters.
– networks of autonomous sensors.
• Advanced Computing Systems (E. Markatos)
– Internet Systems and their Security.
– GRID computing and peer-to-peer systems.
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Sotiriou, ICS-FORTH
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VLSI Group Activities
• Network Processing (I. Papaefstathiou)
– High-throughput packet processing.
– On-the-fly compression and encryption.
• System Timing and Synchronisation (C. Sotiriou)
– Asynchronous circuit/system design
• low-power, low-EMI.
– Asynchronous design using commercial EDA tools.
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Sotiriou, ICS-FORTH
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System Timing Activities
• Coordinators of IST Project ASPIDA (IST-2002-37796).
– ASPIDA.
• (ASynchronous open-source Processor Ip of the Dlx Architecture).
• with Politecnico di Torino and Manchester University.
– Aim: to develop an open-source, low-power, low-EMI, flexibleinterface processor for embedded applications.
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fully-asynchronous CPU (DLX architecture).
may be migrated to any fabrication technology.
industrial quality testability (>95%).
2 processor bus interfaces:
– WISHBONE: synchronous Open on-chip bus (OpenCores).
– CHAIN: novel asynchronous on-chip bus.
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Sotiriou, ICS-FORTH
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System Timing Activities
• members of the ACiD-WG (IST-1999-29119).
– Hosted the 3rd ACiD Workshop.
• Organising the 10th IEEE ASYNC conference.
– More about this at the end!
• Other informal research activities:
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SOC interconnect design (asynchronous).
EDA tool design (mainly synthesis).
EDA flow design.
Asynchronous FPGAs?
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Sotiriou, ICS-FORTH
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Asynchronous Technology?
• EMI Comparison (ARM9 vs. AMULET 3)
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Sotiriou, ICS-FORTH
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Asynchronous Technology?
• Power Density Comparison (Philips 80C51):
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Sotiriou, ICS-FORTH
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Asynchronous Technology?
• Deep SubMicron clocked designs:
– clock distribution issues
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clock tree depth
clock tree power consumption
high ElectroMagnetic Interference (EMI)
clock skew; timing closure problems
– constant reduction of area reachable in 1 clock cycle
– continuous power consumption
– Example Designs
• DEC Alpha 21264: 30-40% power to clock tree
• ARM9TDMI , 220MHz, 32% power to clock tree
• Pentium4 : 20 pipeline stages, 42M trans, 66Watts
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Sotiriou, ICS-FORTH
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ASPIDA: R&D
• R&D activities in ASPIDA:
– asynchronous circuit synthesis from standard HDLs.
– use of commercial EDA tools for asynchronous design
• Cadence, Synopsys based EDA flows.
– automated synthesis of asynchronous Control Circuits.
• relative timed (fast).
• speed independent (robust).
– automated synthesis of asynchronous Datapaths.
– automated scan chain insertion for ATPG
– asynchronous on-chip bus (CHAIN)
• low communication latency.
• no Signal Integrity problems.
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Sotiriou, ICS-FORTH
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ASPIDA: Contribution
ΑDLX
ADLX
HARD IP
SOFT IP
HDL+
flow
Typical SOC
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ASPIDA: CHAIN Interconnect
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Sotiriou, ICS-FORTH
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Collaboration/Ideas
• Collaboration in using/promoting asynchronous technology.
– Using/improving our technology on specific applications:
• mobile and embedded systems.
• low-power, low-EMI systems.
• high performance? scalable asynchronous VLSI systems?
• mixed synchronous/asynchronous systems, interfaces and circuits.
– Comparing with possible alternatives:
• optical clock networks, optical interconnects.
– Develop EDA tools for asynchronous design.
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Sotiriou, ICS-FORTH
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ASYNC 2004
The 10th IEEE International Symposium
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Asynchronous Circuits and Systems
HERSONISSOS, CRETE, GREECE, 19-23 April 2004.
http://www.ics.forth.gr/async2004,
http://www.async04.gr.
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