Transcript ModelSim 6.5 Update Overview

ModelSim DE
™
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ModelSim DE
Leading Single & Mixed Language Simulation
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Native single kernel verification environment
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Verilog 1995, 2001, 2005
VHDL 1987/1993/2002/2008
SystemVerilog for design
SystemVerilog and PSL assertions
SystemC with SCV and TLM, C, C++ (option)
Broadest type support at language boundaries
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Component/module instantiation
SignalSpy™
SC control, observe and connect methods
Only simulator able to share type definitions written in one
package in both VHDL and SystemVerilog
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Preserving full benefits of strong type checking
Mentor Graphics
ModelSim DE 6.5
ModelSim DE
Leading Single & Mixed Language Simulation
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Integrated debug and analysis capabilities
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SecureIP support
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Comprehensive root cause analysis
Coverage analysis and reporting
Commands/GUI consistent across languages, HW platforms
and abstraction levels
Higher performance Xilinx IP
Native support for VHDL and Verilog
Linux and Windows support
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ModelSim DE 6.5
ModelSim DE
Leading Assertion and Coverage technology
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SVA and PSL assertions
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Improved verification effectiveness
Improved time to debug
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Identify failures as they occur
ModelSim DE advanced assertion debugging
Assertion browsing
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OVL assertion library ready
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Code Coverage
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Efficient coverage collection
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Unified Coverage Database (UCDB)
Improve verification test productivity
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Ranking and Merging
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ModelSim DE 6.5
Agenda
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Assertions
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Debug & Analysis
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Coverage
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ModelSim DE 6.5
Assertion Based Verification Improves
Time-To-Bug
Reference Model
Design Under Test
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Lurking bugs:
found late in the
design cycle
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ABV detects bugs at the source, saving valuable debug time
ABV detects bugs missed by top-level test benches
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ModelSim DE 6.5
What is an Assertion?
A concise description of [un]desired behavior
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req
ack
Example intended behavior
“After the request signal is asserted, the
acknowledge signal must come 1 to 3 cycles later”
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ModelSim DE 6.5
Who Uses Assertions?
Functional spec says
ACK will follow REQ
within 7-12 clock
cycles
Hmm.. I assume the
CS inputs are
mutually exclusive
Spec. says that REQ
must not drop before
ACK is received.
Must remember…
This is a 1-hot state
machine
What I really need to
know is how many times
a transfer DOESN’T
complete
Better warn others
about those
checksum gotchas
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ModelSim DE 6.5
Concise and Expressive
SVA Assertion
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req
ack
Example intended behavior
HDL Assertion
property req_ack;
SystemVerilog
@(posedge clk) $rose(req) |-> ##[1:3] $rose(ack);
endproperty
as_req_ack: assert property(req_ack);
always @(posedge req)
Verilog
begin
repeat (1) @(posedge clk);
fork: pos_pos
begin
@(posedge ack)
$display("Assertion Success",$time);
disable pos_pos;
end
begin
repeat (2) @(posedge clk);
$display("Assertion Failure",$time);
disable pos_pos;
end
join
end // always
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ModelSim DE 6.5
ABV Improves Time-To-Coverage
Reference Model
Design Under Test
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ABV reveals internal structural coverage
ABV produces actionable metrics to improve coverage
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ModelSim DE 6.5
Best Time To Bug Resolution
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Assertions identify failure closest to design failure
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Need ability to visualize the assertion
Need ability for root cause analysis
ModelSim DE has the best visualization and debug tools
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Language neutral debug suite
Assertion Analysis
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Waveform Viewing
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S/W logic analyzer
View assertion and it’s signals
Clear indication of assertion status: active/inactive/pass/fail
Assertion animation
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Lists all assertions at current hierarchy
Decomposes assertion for best understanding
Complete user interface tools for root cause analysis
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Source code and graphical dataflow
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ModelSim DE 6.5
Viewing Assertions in the Wave
Green mid-line
indicates assertion is
active
Green triangle
indicates assertion
passed
Red inverted triangle
indicates assertion
failure
Blue low-line
indicates assertion
is inactive
Simply D&D Assertions from Assertion Browser into Wave Window to view assertions
Assertions can be expanded to view all signals associated with the assertion
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ModelSim DE 6.5
View Multiple Assertion Threads
Blue box
above thread
indicates
start of new
thread
RMC on start
of thread box
invokes ATV
Automatic
Thread count
integer
Expand to
see
individual
thread
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ModelSim DE 6.5
Failure Resolution
Assertion Thread Viewer
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Root cause analysis
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Source code
Wave window
Visualize in assertion thread window
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Strategies for Adopting ABV
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Specify design intent
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What I thought I designed
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Identify high-level elements in your blocks:
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Declarations
Key Operations
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Put arithmetic overflow on arithmetic ops
Guard all module I/O
Corner cases
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FIFOs, Arbiters, Memories, FSMs
Make sure test exercises difficult scenarios
Make sure illegal situations are handled correctly
Specify environment assumptions
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What other blocks are doing
Input assumptions
What the testbench should be doing
Avoid debugging false-negative testbench problems
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ModelSim DE 6.5
Agenda
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Assertions
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Debug & Analysis
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Coverage
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ModelSim DE 6.5
Debug All Languages And Analyze Coverage
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Common control
& behavior for all
windows
Consistent look
and feel for all
languages
Root cause
isolation
Coverage
analysis and
reporting
Any window can form
a tab group with any
other window
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ModelSim DE 6.5
Enhanced Wave Window
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Full capabilities
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HDL, SystemC, TLM and
Assertion Debug
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Cross linked with entire
debug environment
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Waveform Compare
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Identify first failure
Logical Views
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Virtual Objects
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Signals, Functions and
regions
Waveform management
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Dataset snapshot, subset,
clear, save, stats
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ModelSim DE 6.5
Wave Window Delta Viewing
Toolbar to control
delta viewing
Same information
in list form
Wave window
expanded to show
delta changes
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ModelSim DE 6.5
User Defined Radix
“push” signals with
& without radix
New radix appears
in pick list
Tcl command
defines radix
radix define States {
11'b00000000000 "NOPUSH",
11'b00000000001 "PUSH1",
11'b00000000010 "PUSH2",
…
11'b10000000000 "PUSH11",
-default hex}
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ModelSim DE 6.5
Wave Window
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Create multiple panes and drag and drop signals from one
pane to the other.
Powerful Edit and Search Capabilities under the Edit Menu.
Cursors - multiple, jump to edge and measurement.
Bookmarks for marking multiple waveform views.
Balloon popup to display values
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ModelSim DE 6.5
Wave Window Analog Display
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Improved analog wave display
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add wave -min and –max
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Example of signal with values between 0 and 5
add wave –analog –min 0 –max 5 –height 100 <my_signal>
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Clamp display to min/max values
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add wave –clampanalog {0|1}
Save with write format wave <file.do>
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ModelSim DE 6.5
Source Annotation
Annotation can be
linked to active cursor
Signal transitions
Steady state values
Hover over signal to get
full path & value
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ModelSim DE 6.5
Textual Dataflow: Tracing Signals
Find reader of strb_r
Select Signal
then RMB
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ModelSim DE 6.5
Textual Dataflow: Tracing Signals
Find driver(s) of prdy_r
Select Signal
then RMB
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ModelSim DE 6.5
Graphical
Dataflow:
Tracing
Signals
Find Cause of Unknown with ChaseX
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Users can also direct dataflow
window to compute and draw paths
between one point and another
Mentor Graphics
ModelSim DE 6.5
Easing Causality Tracing
Source Code Hyperlinking
Enable source code
hyperlinking
Hyperlinked variables
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ModelSim DE 6.5
Easing Causality Tracing
Source Code Hyperlinking
Jump to source window and
highlight variable declaration
Jump through hierarchy
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ModelSim DE 6.5
Expanded Data requires Data Management
Message Viewer
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Organize all simulation messages
Sort by severity or type
Cross links to other windows for quick isolation of
problems
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ModelSim DE 6.5
Agenda
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Assertions
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Debug & Analysis
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Coverage
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ModelSim DE 6.5
Code Coverage
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Measures language coverage
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Have you executed each:
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Best used at block level
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Easier to exercise code
aspects
Ensures blocks are tested &
ready for integration
Built-in
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Statement
Branch
Condition
Expression
Or Toggled each bit
Low overhead
Easy to use
High capacity and performance
UCDB
Improve verification throughput
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Rank UCDB test files and
eliminate regression tests that do
not contribute to coverage
metrics
Comprehensive coverage
exclusion support
Mentor Graphics
ModelSim DE 6.5
Unified Coverage DataBase (UCDB)
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Best capacity and
performance
Most comprehensive
Base technology for
Questa Verification
Management
Verification
Coverage
Analysis &
Reporting
ModelSim
Test
Functional Assertion
Code
Engine
Coverage Coverage
UCDB
Database Toolset, load, copy,
merge, rank, report, analyze
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ModelSim DE 6.5
0-in
Formal
User
Coverage
Test
Specific
3rd Party, Other
Mentor Tools &
User
Data
Plan
Ranking Coverage Results
Per Instance or DU
Include Time based goals
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Merge and analyze regression suite results
Identify highest yield coverage regression tests
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Eliminate non-contributing tests
Mentor Graphics
ModelSim DE 6.5
HTML Coverage Viewing
Specify design
Hierarchy
For details click on
specific Item
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ModelSim DE 6.5
Code Coverage Reporting Efficiencies
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Includes complete coverage result details
Easy reporting to management
Coverage Totals
UCDB/Simulation
Details
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ModelSim DE 6.5
ModelSim DE 6.5 Functional Verification
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The best execution
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The best technology
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Integrated platform available today
Improve verification effectiveness with assertions
The right strategy
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Make every verification cycle count!
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ModelSim DE 6.5
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ModelSim DE 6.5
Additional Mentor Products
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ModelSim DE 6.5
Processor-driven Verification
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Allows test efforts to span multiple stages of the design
- test reuse across the project
Testbench-based
tests
ProcessorDriven C test
High-Level
Simulation
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RTL/Gate
Emulation
Simulation
Prototype
or FPGAs
PostFabrication
Questa Codelink provides the critical features to
support processor-driven, including multi-core
verification
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ModelSim DE 6.5
Hardware/Software Correlation
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ModelSim DE 6.5
Multi-Core Processor Debug Environment
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ModelSim DE 6.5
Mentor’s 0-In® Formal Verification Solution
Delivers …
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Highest capacity and
performance
Extensive Design Style
Support
Smart integration of
formal verification with
simulation
The largest library of assertion IP in the industry
Intuitive graphical analysis and debug
Questa Coverage database enabled
The ‘proven’ formal verification solution
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ModelSim DE 6.5
0-In® CDC Verificaton
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Structural CDC verification
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Verification of CDC protocols
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Automatically identifies all clocks and
clock-domain crossings (CDCs)
Automatically proves CDC Protocols
Simulate CDC protocol assertions
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Silicon-accurate RTL simulation
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Accurate Coverage metrics
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Mimics the metastability effects in
synchronizers
Provides a measure of completeness for
the testbench as related to metastability
issues
0-In® CDC – The Benchmark in CDC verification
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ModelSim DE 6.5
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ModelSim DE 6.5