Transcript A Dual-Loop Injection-Locked PLL with All

Matsuzawa
Matsuzawa
Lab.
A Dual-Loop Injection-Locked PLL with All-Digital PVT Calibration System
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& of
Okada
Lab.
Tokyo Institute
Technology
A Dual-Loop Injection-Locked
PLL with All-Digital PVT
Calibration System
Wei Deng, Ahmed Musa, Teerachot Siriburanon,
Masaya Miyahara, Kenichi Okada, and Akira
Matsuzawa
Tokyo Institute of Technology, Japan
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Outline
• Introduction
• Issues of Conventional InjectionLocked PLLs (IL-PLLs)
• Proposed Dual-loop IL-PLL
• PVT Tracking Capability by Replica Loop
• Low Jitter by Main Loop
• Measurement Results
• Conclusion
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Introduction
• Why High Performance PLL
– Clock generation/distribution
• Key Specifications for SoC Clocking
– Small area
– Low power consumption
– Low jitter
– Scalable with technology advancement
– Insensitive over environment variations
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A Dual-Loop Injection-Locked PLL with All-Digital PVT Calibration System
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Injection-locking Technique
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Injection-locked PLL
[J. Lee, et al., JSSC 2009]
• Reference is injected into VCO through the
pulse generator
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Issue of Injection-locked PLL
Can track
frequency drift
Conventional PLL
Cannot track
frequency drift
Conventional IL-PLL
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A Dual-Loop Injection-Locked PLL with All-Digital PVT Calibration System
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Proposed Dual-loop Architecture
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A Dual-Loop Injection-Locked PLL with All-Digital PVT Calibration System
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Proposed Dual-loop IL-PLL
FCW: Frequency Control Word
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A Dual-Loop Injection-Locked PLL with All-Digital PVT Calibration System
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Calibration Algorithm
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A Dual-Loop Injection-Locked PLL with All-Digital PVT Calibration System
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Phase I: Coarse Freq. Calibration
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A Dual-Loop Injection-Locked PLL with All-Digital PVT Calibration System
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Phase II: Freq. Offset Calibration
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Phase III: Maintaining Operation
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Injection-locked Ring Oscillator
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Chip Microphotograph
80 mm
270 mm
Main
VCO
DAC
Synthesized
Logics
Pulse Generator
DAC
Replica
VCO
Pulse Generator (Dummy)
• Fabricated in CMOS 65nm technology
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Phase Noise
Phase Noise [dBc/Hz]
0
-40
-80
Free Run
-120
Locked
10k
100k
1M
10M
Offset Frequency [Hz]
Ref.: 300MHz (40MHz-300MHz) Freq.: 1.2GHz (0.5-1.6GHz)
Integrated jitter: 0.7ps (10kHz-40MHz) Pdc: 0.97mW (1.2GHz)
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Measured Spectrum
Free-running
1.08GHz
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Locked
1.32GHz 1.199GHz
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1.201GHz
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Spurious at 1.2GHz (Worst Case)
N=12
N=24
Spurious: -38 dBc
Spurious: -31 dBc
N=6
N=4
Spurious: -43 dBc
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Spurious: -49 dBc
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Measured Jitter over Temp.
Single loop
Measured Peak-to-Peak and RMS Jitter [ps]
Dual loop
peak-to-peak jitter
RMS jitter
50
40
30
20
10
0
20
40
60
80
Temperature [oC]
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Performance Summary
This work
IL-PLL
1.2
Freq. [GHz]
(0.5-1.6)
300
Ref. [MHz]
(40-300)
Power [mW]
0.97
Area [mm2]
0.022
Integ. Jitter [ps]
0.7
Jitter RMS/PP
1.81/19.4
[ps]
10M hits
FOM [dB]
-243
CMOS Tech.
65nm
[1]
[2]
MDLL
[5]
IL-PLL
1.6
0.216
DMDLL
1.5
(0.8-1.8)
DPLL
1.5
(0.8-1.8)
375
375
50
27
0.89
0.25
0.4
0.92/9.2
5M hits
-248.46
1.35
0.25
3.2
4.2/33
5M hits
-228.59
12
0.058
0.68
0.93/11.1
30M hits
-233.76
6.9
0.03
2.4
130nm
130nm
130nm
N.A.
-225
55nm
[1] A. Elshazly, et al., ISSCC 2012 [2] B. Helal, et al., JSSC 2008 [5] C. Liang, et al., ISSCC 2011
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Conclusion
• Dual-loop IL-PLL is suited for SoC
clocking
• Low jitter
• Low power consumption
• Small chip area
Dual-loop
• Scalability with process
Injection
locking
All-Digital
FLL
• Insensitivity over PVT
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Acknowledgement
This work was partially supported by
SCOPE, STARC, NEDO, MIC, MEXT,
Canon Foundation, Huawei, and VDEC in
collaboration with Cadence Design
Systems, Inc., and Agilent Technologies
Japan, Ltd.
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Intermit.Calib. at Phase III (1/2)
Step 1: Enable calibration & Replica VCO
Step 2: Disable calibration & Replica VCO
1
10us
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2
1
2
1
2
990us
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Intermit. Calib. at Phase III (2/2)
Step 1: Enable calibration & Replica VCO
Step 2: Disable calibration & Replica VCO
1
10us
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2
1
2
1
W/O Intermittent
1.6mW
W/ Intermittent
1mW
2
990us
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Behavior of Non-ideal Injection
When f0 ≠ N· fref
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Spur Level
Locked state: flocked=N · fref
Free-running: ffree-running=(1+a) · flocked
Spur power
= -20log10((ffree-running- flocked)/(2 ·fref))
= -20log10(a ·N/2)
e.g. N=20, a=0.001  -60dBc spur
[R.B. Staszewski, et al., All-Digital Frequency Synthesizer in Deep-Submicron CMOS, Wiley, 2006]
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FOM over Area
ISSCC 2011 ISSCC 2002
SS-IL-PLL[5] IL-PLL
-220
ISSCC 2011
MDLL
FOM [dB]
-230
-240
ISSCC 2012
IL-AD-PLL
JSSC 2008
MDLL[2]
er
t
t
Be
This Work
IL-PLL
-250
fo
r
Pe
e
c
n
a
rm
ISSCC 2012
DPLL[1]
JSSC 2009
IL-PLL
ISSCC 2009 ISSCC 2012
DMDLL[1] ISSCC 2009
SS-PLL[4]
IL-PLL[3]
JSSC 2009
VLSI 2010
IL-PLL+DDLL
SS-PLL
0.1
0.01
1
Area [mm2]
FOM=𝟏𝟎 𝐥𝐨𝐠
𝝈𝐭 𝟐
𝟏𝐬
·
𝑷𝐃𝐂
𝟏𝐦𝐖
, where 𝝈𝐭 is the integrating jitter
[1] A. Elshazly, et al., ISSCC 2012 [2] B. Helal, et al., JSSC 2008 [3] J. Lee, et al., JSSC 2009
[4] G. Xiang, et al., ISSCC 2009 [5] C. Liang, et al., ISSCC 2011
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PVT Tracking Capability
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IL-PLL with Dual VCOs
Frequency offset between main & replica oscillator
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Injection Timing (Conventional)
[D. Park, et al., ISSCC 2012]
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Injection Timing (Proposed)
 • Injection timing calibration is obliterated
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Proposed Concept
• Dual-loop Topology
– PVT tracking capability
– Compensate for main & replica VCO
frequency offset
– No calibration for injection timing required
• Reduce area & power overhead
• All-digital Frequency-locked Loop
– Compact chip area
– Low power consumption
– Scalable with process advancement
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