Transcript Slide 1

Metallization of Submicron Features
in
High-End Semiconductor Devices by Copper
Electroplating
Uziel Landau
Department of Chemical Engineering
Case Western Reserve University
Cleveland, OH 44106
[email protected]
Presented at ENERGIZER 2/4/05
High-Tech:
• CVD, PVD deposition of semiconductors
• Drugs development
• Catalysis
Technology precedes the science – empiricism
• Electroplating (some aspects)
Low-Tech:
Underlying science is well-established:
• Oil refining
• Electrical machinery
• Steel manufacturing
Outline
• Overview of Copper Interconnect Metallization
• Rationale for this work
• Analyzing the additives effects*
• Experimental Investigations
• Modeling of Additives Transport + Adsorption
• Simulation of the via-fill process
• Scaling Issues & Wafer-scale
• Conclusions
MOORE’S LAWS
1010
108
1G
10-1
256M
128M
10-2
64M
16M
107
Coppermine
Pentium II
4M
Pentium Pro
1M
10
80486
6
256K
10-5
80386
80286
16K
10
10-4
Pentium
64K
105
10-3
4
10-6
4K
8086
1K
10-7
103
8060
4004
1970
1974
1978
1982
1986
1990
1994
1996
2002
10-8
2006
Cost/bit ($,’95)
Transistors / Chip
10
Cost/bit ($,’95)
DRAM
Microprocessor
9
Recent Microprocessors
~ 70 Million transistors/processor
~ 300 Million interconnects/processor
~ 200 Processors/200 mm wafer
Metallized Wafer
Device Speed vs. Size
r
SiO2
Time Constant
t=RC
Interconnect resistance R
L
R 2
r
smaller
Longer Time delay
TRENCH
VIA
GATE
To reduce t • Lower resistivity (ρ)
• Lower dielectric constant (K)
Al
Cu
Ag
2.65 μΩ cm
1.68 μΩ cm
1.59 μΩ cm
DEVICE
GATE
INTERCONNECT
Smaller line size
J. Dahm and K. Monnig, Sematech, AMC 1998 Conf. Proceedings, pp. 3-15.
Interconnect Cross-section
Moving from Al to Cu Interconnects
Al Interconnects
Transistor
‘Gate’
Cu Interconnects
Copper Interconnect Metallization
‘DUAL DAMSCENE’
Routes for copper metallization:
Etch Via
SiN Etch stop
Insulator (SiO2)
Etch Trench
 PVD (0.05-0.1 m/min)
 CVD (0.2 m/min)
 Electroless plating (0.2 m/min)
 Electroplating
(1 m/min)
Electrodeposited
copper
After CMP
PVD
barrier
Copper
seed
Introduced by IBM (Andricacos, Uzoh, Dukovic, Horkans, Deligianni) - 1998
Advantages of Copper Metallization
 Higher conductivity
 Reduced time delay
 Higher current density at lower power
 Scalability – finer lines at lower levels
 Improved EM performance
 Fewer steps – Dual Damascene Process
 Fewer defects
 Less equipment, space
 Lower cost
• Introduced by IBM (Andricacos,
 Faster processing
Uzoh, Dukovic, Horkans,
 Less costly equipment
Deligianni) - 1998
 Environmentally benign
• Commercially implemented (IBM,
Intel, Motorola/AMD, TI,…) - 2001
Issues in Copper Metallization
‘Attitude’ Extending ‘wet chemistry’ to ‘dry’ semiconductor processing
 Doubting the ability of plating to meet the challenge
 Meeting unparalleled requirements of purity and precision
Technical Via scale:
‘Bottom up’ fill
Seed layer in aggressive geometries (<0.2 μm) – continuity
 Wafer scale:
 Thickness uniformity of the copper over-plate
 Resistive substrate (~1000 A seed)
 Modeling and scaling (300 mm, current density, flow…)
 Process Integration
Plating cell
Contact ring
Wafer - Scale Issues
-
Ideal –
Resistive
substrate:
-
Practical
complications
Cell-Design© simulation.
-
500Å Cu seed
( 0.34 /cm)
i ~ 50 mA/cm2
(33 - 344 mA/cm2)
+
k  0.55 S/cm
Flow:
+
Power
perfect
cylinder
• Entrance and exit
• Additives distribution
• Kinetics
Equivalent resistive network
Rseed
Rseed
Vapplied= V+- V- =
= Icenter Relectr.+ Iseed Rseed.
= Iedge Relectr.
vvvvvV
vvvvvV
vvvvvV
Relectrolyte
vvvvvV
vvvvvV
vvvvvV vvvvvV
vvvvvV
vvvvvV
Icenter
vvvvvV vvvvvV vvvvvV
Iedge
vvvvvV
vvvvvV vvvvvV
Icenter
vvvvvV
vvvvvV vvvvvV
Relectrolyte
vvvvvV
vvvvvV
vvvvvV
I EDGE
I
RSEED
 1  SEED
I CENTER
I CENTER RELECTROLYTE
A high resistivity electrolyte will minimize the resistive seed effect
Iedge
+
Low-acid electrolyte
0.6
k   i zi Ci
0.5
K (ohm^-1 cm^-1)
• Typical acid concentration: 0.5 - 2M
• Role of acid: provide conductivity
0.4
0.75 M Cu++
0.3
1.00 M Cu++
1.25 M Cu++
0.2
0.1
0
0
0.25M CuSO4 + 1.8M H2SO4
z 2
C = 0.25x10-3 M/cm3
SO4--:   80
z 2
C = 0.25x10-3 M/cm3
H :
  350
z 1
C = 1.8 x10-3 M/cm3
HSO4-:   50
z 1
C = 1.8x10-3 M/cm3
 Removing the acid; k : 0.5
2
3
Sulfuric Acid Conc. (M)
  54
Cu++:
1
kCu++ = 0. 027 -1cm-1
kSO4-- = 0. 04 -1cm-1
kH+ = 0. 63 -1cm-1
kHSO4-= 0.09 -1cm-1
kTotal = 0.787 -1cm-1
0.05 -1cm-1
Effect of Electrolyte Conductivity
iavg~ 35 mA/cm2
C
L
Electric Contact
SEEDED WAFER
C
L
Electric Contact
SEEDED WAFER
20s
20s
PLATED
COPPER
40s
60s
40s
PLATED
COPPER
80s
80s
100s
100s
Final Copper
Profile
60s
Final Copper Profile
1.8 M H2SO4
1.8 M Sulfuric Acid
Thickness ratio = 1.4
No Acid
No Added Acid
Thickness ratio = 1.1
‘Cell-Design’ © simulations
Flow Simulations
Wafer Scale
60 RPM + 4 GPM Impinging Flow
‘Cell-Design’ Simulations
Flow Simulations
Micro-Scale
Transport within the via
is due to diffusion
‘Cell-Design’ Simulations
Enhancing mass transport
iL 
nFDC B
1 - t  d C
 Flow - reduce d
(but inside via only diffusion pertains...)
 Raise copper conc.: 0.2 - 0.5M
0.85M
(solubility issue -- reducing acid is helpful common ion effect
t (transport number): 0
0.5
Cu zCuCCu
tCu 
  j z jC j
j
New electrolyte formulation
0.0003 ~ 0.1 M (pH = 1~3.5)
– No or low acid 1~2 M (pH=0)
• counteracts the resistive seed effect
• supports higher copper solubility
• ‘chemical’ enhancement of transport
• environmental, safety and handling
benefits
• less corrosive
• enhances copper seed stability in the
presence of dissolved oxygen
0.5 - 1.0 M
– High copper concentration 0.2 - 0.6 M
• enhances transport
Rapid Fill of Vias and Trenches
2-3 Min
< 50 Sec
Gap-Fill Modes
Void

Seam

Conventional
Plating
Conformal
Plating
(unacceptable)
(unacceptable)

Bottom-up
Fill
(Good!)
Via-fill modes
‘Conventional’
Plating
VOID
Conformal
Plating
‘Bottom-up’
Plating
SEAM
Issues in Copper Metallization
• ‘BOTTOM-UP’ plating of vias
“VOID”
“SEAM”
“Bottom-up”
 Special mixture of plating additives can lead to
‘bottom-up’ fill.
 However, additives selection is empirical and
fundamental information about their role is lacking.
What promotes ‘Bottom-up Fill’ ?
• Special plating chemistry required for ‘bottom-up’ fill.
PLATING CHEMISTRY:
~ 0.5 M CuSO4 + H2SO4 + 70 ppm Cl- +
 Polyether (PEG)
‘INHIBITOR’ ~100 – 400 ppm
 Bis(3-sulfopropyl) disulfide (SPS)
‘ACCELERATOR’ ~20 – 50 ppm
 2-imidazolidinethione
~2 – 5 ppm
H-(OCH2CH2)n-OH
Variable Adsorption leads to Variable Kinetics and
to ‘Bottom-up’ fill:
Suppressor,
e.g. PEG
‘Enhancer’, e.g.
Organic di-sulfide
Fast deposition
Slow deposition
Variable Deposition Rates Due to Non-uniform Inhibition
Polarization Curves
i
[mA/cm2]
Enhanced Kinetics (via)
100
Suppressed Kinetics
(‘flat’ wafer)
10
300 mV
V
Key Issues in ‘Bottom-up’ Plating
• All metallization chemistries contain :
• PEG (inhibitor / suppressor)
• SPS (accelerator / anti-suppressor)
• Chloride ions
PEG
+ SPS +
Cl-
=
GOOD
SPS
Cl-
=
BAD
=
BAD
=
BAD
PEG
+
PEG
+
+
SPS
Cl-
WHY ONLY
THESE
and NOT
OTHERS ???
Key Issues
• Accelerated bottom growth should terminate before
top surface is approached
• Top surface must remain passivated for only a
limited time
• Only negligible amount of additives incorporates in
the deposit or decomposes: steady-state models
inadequate
• Via fills in 20-50 s. – Transient interactions are
crucial
• Understanding of transient additives transport,
adsorption, and interactions.
A Few Proposed Mechanisms
IBM’s model
Adjustable
Kinetics
along the
Via Walls
West et al.
Moffat et al.
 2  0
 2C  0
Curvature
Enhanced
Accelerator
Coverage
Diffusion
Controlled
Additives
Transport
Limitations:
Unaddressed Issues:
Unaddressed Issues:
• Steady state model
• Additives interactions
• Unsteady state effects
• Many arbitrary
adjustable
parameters.
• Unsteady state effects
• Role of PEG
•Arbitrary initial
conditions
Objectives
 Characterize the transient additives interactions
 Explain and model the bottom-up fill process
 Develop a Simulation for the Bottom-Up Fill
 Should correlate experimental observations
 Without adjustable parameters or extreme
assumptions
time ?
S
P
P
S
Experimental Setup
Plating Conditions:
• Electrolyte : 0.5 M CuSO4
RDE
+ H2SO4 (pH~2)
Syringe
Cu/CuSO4
Reference
• Galvanostatic : i = 30 mA/cm2
• Rotation speed : 200 rpm
Additives
Additives:
• Chloride ions : 30-100 ppm
• Polyethylene glycol (PEG) : 0-200 ppm
• Bis (3-sulfopropyl)-disodium sulfonate
(SPS) : 0-100 ppm
Copper
plating
chemistry
PEG Adsorption – Effect of Cl260
Overpotential (mV)
240
PEG + Cl-
220
Cl- essential for
PEG assisted
polarization
200
180
160
No
additive
140
Only PEG
120
Only Cl-
100
80
60
0
Injection time
10
20
Time t (s)
30
40
PEG Adsorption
Effect of Concentration
300
200 ppm PEG
Overpotential (mV)
270
240
210
50 ppm
PEG
100 ppm
PEG
180
t ~ L2/D ~ 7 s
150
Cl -
120
PEG saturation
at ≥ 200 ppm
90
0
Injection time
10
20
30
40
Time t (s)
50
60
70
SPS Adsorption on ‘Clean’ Electrode
160
Overpotential (mV)
140
‘Clean’ Electrode
120
50 ppm SPS
+ 70 ppm Cl-
100
80
FAST
ADSORPTION
KINETICS
60
40
20
0
0
Injection time
10
20
30
40
Time t (s)
50
60
70
80
SPS Adsorption on ‘PEG-covered’ Electrode
300
Overpotential (mV)
280
PEG saturated
electrode (+ chloride)
260
240
20 ppm SPS
220
SLOW
depolarization
of the electrode*
t ~ 100 s
200
50 ppm SPS
180
160
140
120
100
0
Injection
time
40
80
120
160
200
240
280
Time t (s)
* R. Akolkar and U. Landau, AIChE Proceedings (2003).
Competitive Adsorption (SPS+PEG)
240
SLOW depolarization
by SPS due to
displacement of PEG
Overpotential (mV)
220
200
180
160
140
FAST polarization
by PEG
120
100
Interactions
dominant during
the via-fill period
(~20-50 s)
80
Injection
time
0
20
40
60
Time t (s)
80
100
Competitive Adsorption (SPS+PEG)
Disc rotation = 50 rpm
80
Current Density (mA/cm2)
70
60
SPS accelerated
kinetics
t=50s
Slow
depolarization
by SPS
50
40
t=10s
t=0s
Time
30
PEG inhibited
kinetics
(short time)
20
10
0
0.00
0.05
0.10
0.15
0.20
Overpotential (mV)
0.25
0.30
Time Scales for Transport,
Adsorption and Interaction
260
240
220
PEG + Cl-
200
V
180
160
140
120
100
PEG
Adsorption
on ‘clean’
electrode
60
0
10
20
SLOW
FAST
(D~10-6 cm2/s) (D~10-5 cm2/s)
VERY FAST
FAST (t~5 s)
Displaces PEG
Cannot displace
slowly
Interaction
SPS
(t~100 s)
30
40
t (s)
300
280
260
20 ppm
SPS
240
220
200
V
Transport
SPS
80
180
160
140
120
100
0
40
80
120
160
t (s)
200
240
280
Via-Fill Model: Initial Surface Coverage
Capillary Flow
High V/A
SPS
PEG
PEG Concentration
Gradient Develops
Low V/A
ADSORPTION on ‘clean’ surface -
Consequently -
• PEG adsorbs rapidly
• All PEG (~100 molecules) adsorbs
• SPS adsorbs slower than PEG
• SPS starts adsorbing on ‘PEG-free’
area
Via-Fill Model: PEG Transport Delay
•PEG diffuses slowly + Adsorbs on
sidewalls
•PEG reaches via bottom after ~10 s
SPS ADSORBS
RAPIDLY ON ‘PEGFREE’ VIA BOTTOM
PEG surface coverage
1.0
 L2
~
DCb R
0.8
t=8s
0.6
t=1s
t=3s t=6s
0.4
0.2
0.0
0.0
TOP
0.2
0.4
0.6
0.8
Normalized Depth z*
1.0
BOTTOM
*Via is 0.1 μ dia.,1 μ deep
Via-Fill Model: PEG Transport Delay
MORE PEG
Coverage
MORE SPS Coverage
Accelerated
Bottom-up
Growth
*R. Akolkar and U. Landau, J. Electrochem. Soc., 151 (11) C702 (2004)
Modeling of Via Fill
Time Dependent Transport Kinetics (‘TTK’) Approach
Via Exterior (I)
Via Interior (II)
BULK
I
VIA
TOP
I
Electrolyte
II
Wafer
Surface
1μ
0.1 μ
Solve for C ( z , t ) and θ ( z , t ) in I and II
VIA
BOTTOM
Modeling of Via Fill – TTK Approach
Additives Transport to the WAFER TOP SURFACE
BULK PEG
Concentration
Profile given by :
DPEG
d 2 C PEG dC PEG

2
dz
dt
Diffusion
boundary layer
NO CONVECTION
60 μ
WAFER TOP
SURFACE
Adsorption = k ( 1 – θ )
small features
are neglected
Via Exterior: Flat wafer surface
PEG surface coverage
1.0
0.8
PEG inhibits flat wafer
surface instantaneously
(t ~ 3-4 s)
0.6
0.4
0.2
0.0
0
1
2
3
4
Time t (s)
5
6
7
Modeling of Via Fill*
Additives Transient Processes INSIDE THE VIA
Diffusion IN
OUT
R = 0.1 μ
L =
1μ
Adsorption on
the sidewalls
Model incorporates (NO Adjustable Parameters):
• Additives Transport (PEG diffusion)
• Adsorption on sidewalls (Kinetics)
• Additives Interactions (SPS displaces PEG)
*R. Akolkar and U. Landau, Abstract No. 157-E1, 205th ECS Meeting, San Antonio (2004).
Modeling of Via Fill – TTK Approach
Transport and Competitive Adsorption of both PEG & SPS
Ni,A
Diffusion IN Ni,T
N iT  - Di
Ci
z
Ni,D
OUT
z
z+z
z=0
Ni,T=0
z=L
PEG Adsorption :
A
NPEG
 kPCP 1-P -S 
SPS Adsorption :
A
NSPS
 kS CSB 1 - P - S 
PEG Displacement:
NPD  -k3CSbP
SPS ‘Intreractive’
Adsorption :
S
N 
k3CSb P
P
D
S
Modeling of Via Fill*
Additives Transient Processes INSIDE THE VIA
Adsorption
Diffusion IN
R = 0.1 μ
OUT
DIFFUSION
L =
1μ
ADSORPTION
PEG
Transport
CP
 2 CP 2
b


 DP
k
C
(1


)
k
C
P P
P
S
3 S P 
2

t
z
R
PEG
Coverage
 P
1
kPCP 1 -  P -  S  - k3CSb P 

t
P
SPS
Coverage
 S
1
1

kS CSb 1 -  P -  S  
k3CSb P
t
S
P
PEG-SPS
INTERACT
*R. Akolkar and U. Landau, Abstract No. 157-E1, 205th ECS Meeting, San Antonio (2004).
Additives-Assisted Deposition Kinetics
Cu++
Cu
iSPS
SPS
Cu
PEG
i
iCu
PEG
COPPER SURFACE
Modulated
current
density
  jF 
i j  io , j j exp  
 Rg T 
Additives-Assisted Deposition Kinetics
Cu
PEG
 PF 
 io , P P exp  
 Rg T 
Cu
SPS
 S F 
 io , S S exp  
 Rg T 
Cu++
Cu
iSPS
Cu
iPEG
i Cu
i
SPS
PEG
i
COPPER SURFACE
Cu
Cu
i
Total current density:
Deposit thickness:
  F 
 io , (1 -  P -  S ) exp  
 Rg T 
itot  i
Cu
PEG
h M Cu itot

t
F n
i
Cu
SPS
i
Cu
Cu
ADDITIVES COVERAGE AT SHORT TIMES
1.0
1.0
0.8
SHORT TIMES
0.6
0.8
0.6
PEG-1s
0.4
0.2
0.4
SPS
TRANSPORTADSORPTION
PROCESS
(0 < t < 5 s)
0.0
0.0
High PEG
VIA
Low SPS
TOP
0.2
SPS-1s
0.4
0.6
Distance Into the Via
0.8
0.2
SPS Surface Coverage
PEG Surface Coverage
PEG
0.0
1.0 Low PEG
VIA High SPS
BOTTOM
1.0
1.0
0.8
0.8
SHORT TIMES
0.6
0.6
PEG-3s
0.4
0.2
0.0
0.0
VIA
TOP
TRANSPORTADSORPTION
PROCESS
(0 < t < 5 s)
0.2
0.4
SPS-3s
0.2
0.4
0.6
Distance Into the Via
0.8
0.0
1.0
VIA
BOTTOM
SPS Surface Coverage
PEG Surface Coverage
ADDITIVES COVERAGE AT SHORT TIMES
1.0
1.0
0.8
0.8
SHORT TIMES
PEG-5s
0.6
0.4
0.2
0.6
0.4
TRANSPORTADSORPTION
PROCESS
(0 < t < 5 s)
0.0
0.0
VIA
TOP
0.2
SPS-5s
0.2
0.4
0.6
Distance Into the Via
0.8
0.0
1.0
VIA
BOTTOM
SPS Surface Coverage
PEG Surface Coverage
ADDITIVES COVERAGE AT SHORT TIMES
1.0
1.0
0.8
0.8
PEG-5s
0.6
0.6
PEG-1s
PEG-3s
0.4
TRANSPORT0.2 KINETICS REGIME
(0 < t < 5 s)
0.0
0.0
VIA
TOP
0.2
0.4
0.4
SPS-5s
0.2
0.6
Distance Into the Via
0.8
0.0
1.0
VIA
BOTTOM
SPS Surface Coverage
PEG Surface Coverage
ADDITIVES COVERAGE AT SHORT TIMES
PEG COVERAGE AT LONG TIMES
PEG Surface Coverage
1.0
time
10 s
0.8
0.6
0.4
PEG displacement
by the SPS
40 s 30 s
(t~100 s)
0.2
0.0
0.0
VIA
TOP
INTERACTION
REGIME
(5 < t < 100 s)
0.2
0.4
0.6
0.8
Distance Into the Via, z*
1.0
VIA
BOTTOM
SPS COVERAGE AT LONG TIMES
SPS Surface Coverage
1.0
0.8
INTERACTION
REGIME
(5 < t < 100 s)
0.6
0.4
SPS displaces the
10 s
adsorbed PEG
(t~100 s)
30 s
20 s
0.2
0.0
0.0
VIA
TOP
time
0.2
0.4
0.6
0.8
Distance Into the Via, z*
1.0
VIA
BOTTOM
SPS - Comparison: Via Top vs. Via Bottom
0.3
SPS Surface Coverage
VIA BOTTOM
SPS adsorbs on ‘PEGcovered’ bottom
0.2
SPS adsorbs
on ‘PEG-free’
bottom
0.1
0.0
VIA TOP
TRANSPORT-KINETICS
INTERACTIONS
0
10
20
Time (s)
30
40
PEG - Comparison: Via Top vs. Via Bottom
1.0
PEG Surface Coverage
VIA TOP
0.8
0.6
SPS displaces the
adsorbed PEG
0.4
VIA BOTTOM
PEG diffuses to
the via bottom
0.2
0.0
TRANSPORT-KINETICS
INTERACTIONS
0
10
20
Time (s)
30
40
Effect of PEG Transport Delay
• Flat RDE used to simulate transport to the via
Kinetic Resistance (ohm)
30
Simulated via top
Flow affects
(i=15 mA/cm2,
PEG transport
200rpm)
25
only
20
15
10
Simulated via bottom
(i=30 mA/cm2, 90rpm)
5
Slow PEG
transport
allows SPS
time to adsorb
0
0
Injection
time
20
40
Time t (s)
60
80
100
COMPARISON: Via Top vs. Via Bottom
1.0
0.8
LONG
TIMES
VIA BOTTOM
0.6
SPS displaces the
adsorbed PEG
0.4
RDE Experiments
30
Corresponds to
via top
25
PEG diffuses to
the via bottom
0.2
Kinetic Resistance
PEG Surface Coverage
VIA TOP
20
15
Corresponds to
via bottom
10
0.0
0
10
Time (s)
20
30
5
40
0
0
20
40
60
Time (s)
*R. Akolkar and U. Landau, J. Electrochem. Soc., submitted.
80
100
Effect of varying surface area
on additives coverage
• Surface area at via bottom shrinks
• PEG bonds weakly and re-equilibrates with the electrolyte
• SPS bonds strongly and does not leave surface
• SPS (or PEG) do not incorporate appreciably within the deposit
Material balance on SPS:
TK
new
AinitSPS
t   At SPS
t 

new
SPS
Ainit TK
 SPS  t 
t  
A t 
SURFACE AREA REDUCTION effects
SPS Surface Coverage
on the via bottom
1.0
SPS
saturation at
the bottom
SPS Coverage
from transport
modeling + Area
Reduction Effects
0.8
0.6
SPS Coverage
predicted by
Transport-Kinetics
model alone
0.4
0.2
0.0
0
1
2
3
4
Time (s)
5
6
7
A. C. West, S. Mayer and J. Reid, Electrochem. Solid-State Lett., 4 (7), C50 (2001).
T. P. Moffat et al., Electrochem. Solid-State Lett., 4 (4), C26 (2001).
8
EFFECT OF LOCAL AREA REDUCTION
PEG Surface Coverage
on the via bottom
1.0
PEG Coverage
predicted by
Transport-Kinetics
approach alone
0.8
PEG Coverage
accounting for
the Local Area
Reduction
0.6
0.4
Complete
Removal
of the PEG
0.2
0.0
0
2
4
Time (s)
6
8
Modeling the ‘Bottom-up’ Fill*
t=0s
PEG
SPS
Uniform
additives
composition
everywhere
* R. Akolkar and U. Landau, J. Electrochem. Soc., accepted for publication.
Modeling the ‘Bottom-up’ Fill
t → 0+ s
Fast inhibition
on the flat
wafer
PEG
SPS
Fast adsorption
of PEG on via
sidewalls
Modeling the ‘Bottom-up’ Fill
t = 1-2 s
SPS diffuses
fast – 20
times faster
than PEG
PEG
Inhibited
wafer
surface
Fast transport of
PEG to upper via
sidewalls
SPS
Fast diffusion and
adsorption of SPS
on ‘bare’ copper
Modeling the ‘Bottom-up’ Fill
t ~ 10 s
PEG
SPS
Inhibited wafer
surface and via
sidewalls
PEG cannot
polarize SPS
covered surface
Modeling the ‘Bottom-up’ Fill
t ~ 50 s
PEG
SPS
SPS slowly
depolarizes the
wafer surface by
displacing PEG
Summary of Key Aspects of ‘Bottom-up’ Fill
• No additives initially inside the via due to the
low volume/area ratio.
• High volume/area ratio on the wafer top surface
leads to instantaneous inhibition by PEG.
• Slow transport of diffusion limited PEG to the
via bottom ( t ~ 8-10 s ).
• The PEG transport delay allows time for fast
diffusing SPS to adsorb on the via bottom.
• Delayed arrival of PEG cannot displace the
stronger adsorbing SPS.
Scaling Analysis of Additives Transport
Why is a via with ‘reactive sidewalls’
associated with a large PEG transport delay ?
Time constant
t ~ L2/D
PEG is transported
by diffusion from
the bulk into the via
For a 1 μ via, the
time constant
t ~ 0.02 s
No PEG inside the
via at t ≈ 0 due to
small V/A ratio
PEG Transport Delay
Numerical Simulation of PEG Transport
0.7
Non-reactive
Sidewalls
PEG surface coverage
at via bottom
0.6
0.5
0.4
Reactive
Sidewalls
0.3
PEG transport
delay: no PEG at
via bottom for ~8 s
0.2
0.1
0.0
0
2
4
Time (s)
6
8
10
Scaling Analysis
One-dimensional Pseudo Steady-State Model
Uniform inhibition on
the sidewalls
2R Infinite Sink at
Via Bottom
L
d 2CPEG
2
m
CPEG  0
Transport-Adsorption Model :
2
dz
•Short times – Low θ – High k, μ
2
2kL
m2 

RD
•Long times – High θ – Low k, μ
Thiele Modulus
k, μ depends on time –
“μ decreases with time”
where :
Adsorption Rate
Diffusion Rate

k  ko 1 -  avg

One-dimensional Transport Kinetics Model
Approach
Concentration Profiles
μ=1
Decreasing ‘μ’
μ = 30
due to gradual
inhibition of
sidewalls
No Transport of
PEG to the
Bottom at high μ’s
1
PEG Concentration, C*
Scaling
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
Normalized Depth, z*
Via Top
Via Bottom
Establishing Relationship Between k and t
In time t :
Amount of PEG
Amount of PEG
+
Entering the Via = Adsorbed on
the Sidewalls
Amount of PEG
Accumulated in
the via
Assumptions :

Negligible PEG Accumulation

Average Diffusion Flux In :
 Cb 
N  D 
 L2 
Linear Time Dependence of k :
  DCb R  
k  ko 1 - 
t
2  
  L  
PEG Transport Delay
Scaling
Normalized Flux of PEG
at the via bottom
0.20
Approach
0.16
0.12
0.08
PEG transport
delay: no PEG at
via bottom for ~9 s
0.04
0.00
0
Uninhibited
via sidewalls
θside= 0
2
4
Time t (s)
6
8
10
12
Inhibited via
sidewalls and
bottom θ ~ 1
PEG Transport Delay
Effect of Via Radius (L=1 μm)
PEG Transport Delay (s)
30
 PEG
25
    L2 

 
 DCb   R 
20
Inverse dependence
of PEG transport
delay on via radius
‘Transients’ due to
Transport Kinetics
significant for high
aspect ratios
15
10
INTEL 90nm
technology
5
0
0
High Aspect
Ratio Vias
0.2
0.4
0.6
Via Radius (μm)
0.8
1
Low Aspect
Ratio Vias
PEG Transport in Vias with Sloping Sidewalls
How does the via geometry affect the PEG
transport characteristic ?
2Ro
2Ro
Ф
Ф = positive
(Outward
Sloping)
RE-ENTRANT
2Ro
Ф
Ф=0
(Non-Sloping)
Ф = negative
(Inward
Sloping)
One-dimensional Unsteady-State Model
kC 1 -  
Adsorption
Diffusional
Flux IN
OUT
-D
dC
dz
Adsorption
Ф>0
Ф<0
Transport Model for a Via with Sloping Reactive Sidewalls :
Diffusion IN = Diffusion OUT + Adsorption + Accumulation
Diffusion =
Adsorption =
dC
 r 2 
dz
~ r2
kC 1 -   2 rL
~ r1
-D
Effect of
varying radius
stronger on
transport
One-dimensional Unsteady-state Model
Surface Coverage at the
via bottom (θPEG)
0.6
Ф=0o
0.5
FASTER
Transport
Ф = 10 o
0.4
Ф = -1.1 o
0.3
0.2
SLOWER
Transport
0.1
0.0
0
2
4
Time t (s)
6
8
10
Quantitative Modeling of Via-Fill
Time Scales
SHORT
Transport-kinetics
time scale
LONG
Additives Interaction
time scale
t ≤ 10 s
PEG
SPS
t > 10 s
Transport Kinetics Time Scale
SHORT t ≤ 10 s
 Generation of differential
plating kinetics between
the via top and bottom –
initiation of superfill.
PEG
SPS
 Copper deposition
preferentially occurs at
the via bottom.
Simulation of Via-Fill
• Requires additives distribution
• Effect of additives surface coverage on the kinetics
• NUMERICAL APPROACH
• Solution of the Nernst-Planck Equations or a
simplified case (Laplace’s Equation)
• Time stepping moving boundary
• SEMI-QUANTITATIVE APPROACH
• Neglect concentration variations inside the via
• Move electrode boundaries on the basis of local
kinetics using Faraday’s law
Simulation of Deposit Propagation
Variable kinetics + Moving boundaries
Virtual electrode;
Outer edge of diffusion layer
 2  =0
i = f (η)
 2 C =0
dC
Passivated kinetics (PEG->SPS)
Variable kinetics
[Partially passivated, f(t)]
Accelerated kinetics (SPS)
Numerical Simulation of
Via-Fill – Variable Kinetics*
Electrolyte
Electrolyte
Fill Time: 48 sec.
Overpotential: - 124 mV
Bottom:
i = 60 mA/cm2
Top:
‘Cell-Design’
Simulations
MOVING
BOUNDARIES
i = 0.24 mA/cm2  3.4 mA/cm2
(Depolarization by SPS)
Sidewalls: Interpolated kinetics
between Top and Bottom
* U. Landau, E. Malyshev, R. Akolkar and
S. Chivilikhin, AIChE Proceedings (2003).
SiO2
SiO
2
Via Fill Simulation
Current density has been lowered:
 No Bottom-Up Fill
Electrolyte
Plating Time: ~147 sec.
Overpotential: - 80 mV
Bottom:
i = 10 mA/cm2
i0 = 1.12 mA/cm2
C = 0.83
Seam
Top:
i = 0.05 mA/cm2  4.8 mA/cm2
High Depolarization by SPS:
i0 = 3.1 μA/cm2  0.28 mA/cm2
C = 0.9
Sidewalls: Interpolated kinetics
between Top and Bottom
1 sec
time
intervals
‘Cell-Design’ Simulations
SiO2
SIMULATIONS OF THE VIA-FILL
1.2
z*
1.0
η = 120 mV
0.8 PEG = 100 ppm
SPS = 20 ppm
35 s
30 s
0.6
0.4
20 s
Flat ‘Bottom0.2
up’ Growth
iavg=63 mA/cm2
0.0
-0.6
-0.4
-0.2
10 s
0.0
0.2
r*
*V. Dubin, Microelectronic Engineering, 70, 461, 2003.
0.4
0.6
VIA-FILL
VIA-FILL SIMULATIONS: Effect of SPS
1.2
η = 120 mV
PEG = 100 ppm
SPS = 0 ppm
1.0
0.6
0.4
Seam
after
900 s
‘Conformal
Deposition’
1.2
0.2
0.0
-0.6
1.0
-0.4
-0.2
0.0
r*
0.2
0.4
0.6
z*
z*
0.8
0.6
0.4
η = 120 mV
PEG = 100 ppm
SPS = 100 ppm
15 s
0.8
0.2
‘Centerline’
Voids
Rapid
depolarization
on the via
sidewalls
0.0
-0.6
-0.4
-0.2
0.0
r*
0.2
0.4
0.6
Growth Profile at Low overpotential
1.2
1.0
η = 80 mV
0.8 PEG = 100 ppm
SPS = 20 ppm
BAD
z*
0.6
Seam
after 75 s
1.2
0.4
0.2
1.0
Bottom cannot
0.8
escape depolarizing
0.6
sidewalls
GOOD
Low ‘bottom-up’
current density
i ~ 12 mA/cm2
0.0
-0.6
0.4
0.2
-0.4
-0.2
0.0
r*
0.2
0.0
-0.6
0.4
-0.4
-0.2
0.6
0.0
0.2
0.4
0.6
Modeling of Superfill – Effect of Current Density
Cpeg=200 ppm
Csps=20 ppm
Via AR = 10
V = 130 mV
V = 60 mV
1.2
1.2
200 s
30 s
Bottom-up
growth
1
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
21 mA/cm2 0
-0.2 -0.1 0
0.1 0.2
0
-0.2 -0.1
‘Seam’ at
the mouth
due to
depolarizat
ion by SPS
1 mA/cm2
0
0.1 0.2
Wafer-scale Modeling
• Rationale for study
• Only wafer-scale parameters,
e.g., total current (I) or voltage (V)
are measurable
• Optimize the process by identifying current/
potential waveforms
Transient nature of wafer-scale processes due to:
• Transient additives interactions
• Geometry changes during via-fill
Wafer-scale Modeling
300 mm wafer
0.2 μ dia., 1 μ deep vias
(via loading ~ 6 %)
Empirical observations during wafer metallization:
• Current is initiated upon wafer immersion
• Initial overall current is low
• Current is increased as via-fill is initiated
Wafer-scale Modeling
itop
ibottom
Current balance on the entire wafer :
I wafer  itop Atop  iside Aside  ibottomAbottom
Assuming inhibited sidewall kinetics similar to the wafer top
I wafer  itop Atop  Aside   ibottomAbottom
The wafer geometric current density :
iwafer 
I wafer
Ageometric
Wafer-scale current transients
10
η = 0.12 V (constant ‘Driving force’)
12
8
10
Wafer current drops
at long times (t>25s) 6
8
6
Rapid wafer
depolarization
at short times
(t < 10 s)
4
2
4
2
SPS = 20 ppm
PEG = 100 ppm
0
0
0
5
10
15
20
Time, s
25
30
35
Wafer Current, A
Wafer Current Density, mA/cm2
14
Wafer Current Density, mA/cm2
Comparison with Experiments
14
Model predictions in agreement with
12 experiments
10
Source: J. Reid et. al.*
8
6
4
2
0
0
5
10
15
20
25
30
35
Time, s
* Experimental data: J. Reid et al., Electrochem. Solid-State Lett., 6(2) C26 (2003).
Wafer Current Density, mA/cm2
Wafer-scale i vs. t : Effect of potential
16
η = 0.13 V
14
12
10
8
VIA-FILL
COMPLETION
η = 0.12 V
6
4
SPS = 20 ppm
PEG = 100 ppm
Via loading = 6.3%
2
0
0
5
10
15
20
Time, s
25
30
35
Wafer Current Density, mA/cm2
Wafer-scale i vs. t : Effect of SPS conc.
18
16
SPS = 30 ppm
Centerline Voids
14
12
10
8
SPS = 20 ppm
‘Defect-free’ Fill
6
4
η = 0.12 V
PEG = 100 ppm
Via loading = 6.3%
2
0
0
5
10
15
20
Time, s
25
30
35
Wafer Current Density, mA/cm2
Wafer-scale i vs. t : Effect of via loading
18
Via loading = 12.6%
16
14
12
10
Via loading = 6.3%
8
6
4
η = 0.12 V
PEG = 100 ppm
SPS = 20 ppm
2
0
0
5
10
15
20
Time, s
25
30
35
Implication of Constant Current
10
η = 0.12 V (constant ‘Driving
force’)
12
Current
8
10
6
8
Voltage
14
6
10
4
4
SPS =` 20 ppm
PEG = 100 ppm
2
2
0
0
0
5
10
15
20
Time, s
25
30
35
Wafer Voltage (mV )
Wafer Current Density, mA/cm2
14
12
Too high – bottom defects
8
10
6
8
120
6
4
4
2
Too low– centerline
defects
2
0
0
0
5
10
15
20
Time, s
25
30
35
Major Conclusions
• A comprehensive model for the ‘bottom-up’ fill is
presented.
• WITHOUT invoking any adjustable parameters
• Based on experimentally characterized
additives effects
• The model explains:
• Specific role of the PEG and SPS in the multicomponent additives system
• The effect of operating parameters and via
geometry
• Wafer-scale current response.
Acknowledgements:
 Dr. Rohan Akolkar
 Case Prime Fellowship to Rohan Akolkar
 General Motors Research and Development
 The Dept. of Chemical Engineering, CWRU
• John D’Urso
• David Rear
• Mark Bubnick
 Applied Materials
• Yezdi Dordi
• Peter Hey
THANK YOU ALL!
Additives Distribution during TK time scale
1.0
1.0
0.8
0.8
0.6
0.6
No PEG or SPS
on the via
sidewalls at t = 0
0.4
0.4
0.2
0.0
0.0
Via Top
0.2
0.2
0.4
0.6
0.8
Normalized depth, z*
SPS Surface Coverage
PEG Surface Coverage
t=0s
0.0
1.0
Via Bottom
Additives Distribution during TK time scale
1.0
1.0
0.8
0.8
Inhibited
0.6 Via Top
0.4
0.6
PEG-free
bottom with
some SPS 0.4
0.2
0.2
0.0
0.0
Via Top
0.2
0.4
0.6
0.8
Normalized depth, z*
SPS Surface Coverage
PEG Surface Coverage
t<1s
0.0
1.0
Via Bottom
Additives Distribution during TK time scale
1.0
1.0
0.8
0.8
0.6
Inhibited
Via Top
Accelerated
Via Bottom
0.6
0.4
0.4
0.2
0.2
0.0
0.0
Via Top
0.2
0.4
0.6
0.8
Normalized depth, z*
SPS Surface Coverage
PEG Surface Coverage
t~4s
0.0
1.0
Via Bottom
Additives Distribution during TK time scale
t~8s
1.0
0.8
0.6
0.8
0.6
High PEG
Low SPS
0.4
0.4
0.2
0.2
0.0
0.0
Via Top
Low PEG
High SPS
0.2
0.4
0.6
0.8
Normalized depth, z*
SPS Surface Coverage
PEG Surface Coverage
1.0
0.0
1.0
Via Bottom