Transcript Diapositiva 1 - Istituto Nazionale di Fisica Nucleare

Introduction to the TRAMS project
objectives and results in Y1
Antonio Rubio, Ramon Canal
UPC, Project coordinator
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Global objective of TRAMS
The TRAMS vision for reliable, cost-efficient tera-device multicores powering
high performance future, safety-critical applications
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Structure
Bulk-cmos sub-22nm
Finfets
CNT
Others (MIM, RRAM, PCM …)
Mitigation, adaptive, and
tolerant mechanisms
Multi-core architectures
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
M0
Y1(M12)
Y2(M24)
D5.1
web
MS1
Variability and reliability bulk cmos
device level
D1.1, D2.1,D3.1, D4.1,D5.1,D5.2, D3.6
circuit level
MS2
Variability and reliability Findfets and CNT
Mitigation, compensation, redundant and
reconfiguration mechanims
MS3
MS4
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Si-bulk
Work in Y1
CNFET
6T
1T1C
3T1D
Device level: 65,45,32,22,16, Si-CMOS public models
18 and 13 nm Si-CMOS from WP1
CNFETS (n=8), equivalent to 16nm
Circuit level:
Bit-cell types: 6T, 1T1C, 3T1D
32 kB cache circuit: both 6T and 3T1D.
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Process variability
at device level
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Bit-cells:
6T bit-cell
3T1D bit-cell
1T1C (32) bit-cell
32 kB cache:
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
IMPACT OF DEVICE
VARIATIONS ON MEMORY
PERFORMANCE DRIFT
Significant impact on
performances of speed
AND a dramatic drop in
reliability (catastrophic
Failures)
Prediction of null yield
With conventional
implementation
methods
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Circuit level
Conclusions
• Temperature is a key environmental factor, that may cause an increase until a
60% in read/write time cycles, both S and DRAM.
• Temperature is a very limiting factor in DRAM, reducing the retention time
around 1/50.
• Temperature is an inherent factor, significant in these technologies, possibilities
to sense T and actuate with different adaptive mechanisms.
• Voltage fluctuations and systematic manufacturing variability are the
responsible of 15 and 10% delay fluctuations. Can be partially alleviated at
design (layout and circuit level).
• Reliability characteristics are dramatically impacted by process random variations
(higher in 6T and 1T1C than in 3T1D but dramatic for both) (null yield), as well
as aging BTI (degeneration) and SEU.
• New challenging alternatives to implement complex systems have to be investigated.
• Potentially future technologies, as CNFET and others, will offer interesting
alternatives in memory design
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Conclusions
In Y2 (second year) TRAMS project will work on
the analysis of alleviating mechanisms for
systematic process variations and voltage
fluctuations, at layout and circuit level. About
temperature we will investigate on innovative
adapting and compensation mechanisms, with
the use of sensors and knobs, similar solution
will be applied to attenuate the effect of aging
caused by BTI. For process variations we will
investigate the trade-off between mitigation
solutions at design level and the resulting
performances. For moderate and high
catastrophic and transient failures we will
investigate new redundancy and error codes
insertion techniques . And even for high and
very high catastrophic and transient failures we
will investigated hierarchic significantly
redundant tolerant architectures.
Inclusion of Finfet and CNTFET technologies.
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011
Thanks for your attention!
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17th-18th 2011