Transcript TRAMS - Euretile
Carbon Nanotube Technology An Alternative in Future SRAM memories UPC
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Introduction
• In Si-bulk CMOS technology the variability of the device parameters is a key drawback and it may be a limiting factor for further miniaturizing nodes.
•
OBJECTIVE
: to evaluate the variability in Carbon nanotube Field Effect Transistor (CNFET) as well as its real capability to be a promising alternative to Si-CMOS technology. 1. Impact of carbon nanotube (CNT) diameter variations and the presence of metallic CNTs in the transistor (device level).
2.
Comparison between Si-CMOS and CNFET 6T SRAM cells (circuit level).
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Device level
Carbon Nanotubes (CNTs)
Carbon nanotube Chiral vector angle of the atom arrangement along the tube Graphene
C h
=
na
1 +
ma
2 º (
n
,
m
)
Diameter
D CNT
= 3
a
0 p
n
2 +
m
2 +
nm a
0 = 0.142
nm
Behaviour
[ (
n
-
m
) /3 ] = 0 Rest of [ (
n
-
m
) /3 ] ¹ 0 th -18 th 2011 Metallic Semiconducting
Device level
Carbon Nanotube Field Effect Transistors (CNFETs)
An “Ideal” MOSFET-like CNFET is formed by 1 or more semiconducting CNTs perfectly aligned and well-positioned whose section under the gate is intrinsic and the s/d extension regions are n/p doped.
Promising candidates to replace silicon CMOS due to its high performance
There are some imperfections inherent to CNT synthesis and CNFET manufacturing process that may eclipse the expectations
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Device level
SOURCES OF VARIATION
CNT growth process CNFET manufacturing process
NO control of chirality
• Percentage of m-CNTs • Diameter variations • S/D doping variations • Mispositioned and misaligned CNTs Semiconducting CNTs Metallic CNTs CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Device level
CNFET device model [1]
Fixed parameters Power supply Oxide thickness
0.9V
4nm
Gate/Source/Drain length (CNT)
16nm
Width of the metal gate CNT pitch
36nm 4nm
Variable parameters Number of CNTS per device (N) CNT diameter (D) Metallic CNT proportion (T M )
Nominal:8 Range:4-12 1-6 nm Chi distribution 0% - 33% [1] J. Deng and H.-S. Wong, “A compact spice model for carbon-nanotube field-effect transistors including nonidealities and its application part II: Full device model and circuit performance benchmarking, ” Electron Devices, IEEE Transactions on, vol. 54, no. 12, pp. 3195 –3205, 2007.
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Monte Carlo experiment
Device level
Example of I DS − V DS distribution for 50 CNFET samples.
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
STD (σ) of V
TH
and K
Device level P ercentage of variation (100x3σ/μ)
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Circuit level Variability analysis and performance in CMOS and CNFET SRAM 6T cells PTM
Technology 32nm 22nm
T
16nm 11nm
V DD
1V 1V
TRAMS WP1
16nm 18nm 8nm 9nm 1V 0.7V
13nm 0.7V
CNFET
8 tubes 6.5nm W=32nm, L=16nm 1V CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Circuit level
CNFET SRAM cell versus Si-MOSFET SRAM cell (nominal comparison)
60 40 20 0 160 140 120 100 80
22.28
105 19.44
87.01
16.73
73.15
23.42
139.8
20.97
95.76
7.77
57.42
Write me (ps) Access me (ps) 32nm 22nm 16nm 18nm 13nm CNFET
Static Power (pW) Dynamic power (
m
W) Read SNM (mV) Cell area (
m
m 2 ) PTM
296 0.29 262.90 218 0.14 0.09
TRAMS WP1 CNFET 32nm 22nm 16nm 18nm 13nm 8 tubes
109.60 112.40 279.60 11.39x10
6 8.11x10
6 5.82 7.17 4.91 3.94 1.53 1.26 3.06 202.80 0.07 195.50 0.045 302.50 0.09 CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Circuit level
CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison)
CNFET Technology NCNFET V TH
m
(V)
0.12
s
(V)
0.0187
PCNFET V TH
m
(V)
-0.12
s
(V)
0.0187
Random 6T cell 100 x 1
s
/average V TH
15.58% CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Circuit level
CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison)
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Circuit level
CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison)
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Device level
Conclusions
• CNFETs are promising candidates to replace Si-MOSFETs due to their high current driving capability, tolerance to temperature and low leakage currents.
• Manufacturing variability, that is one of the key limiting factors in silicon-MOS technology, has been investigated for such CNFET devices.
• Considering a range of metallic tubes from 33% (current growth methods) to 0% (perfection) and a realistic distribution of diameters, it has been shown that the variability of both K factor and V TH is lower than CMOS for transistors with just 8 nanotubes, and much better for 12 tubes.
• In a future scenario with a narrower distribution of CNT diameters, variation for both parameters could reach levels from 15% to 25%, fact that would allow a design procedure without the stress caused by variability in current conventional technology.
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Circuit level
Conclusions
• CNFETs can be also considered as a potential alternative to CMOS in memory systems.
• CNT technology presents better performance than CMOS technologies. However the implementation maturity of CNFET is still pending of several years of development. • Variability analysis shows as a promising prospect, that even for todays CNFETs performance, its variability is comparable with that of Si-MOS technology in a scenario which we have called ”moderated”.
• Therefore, improvements in the control of chirality, the variability of CNFETs could be lower than in that moderated scenario.
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Thanks for your attention!
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Carbon nanotube Graphene
Device level
Carbon Nanotubes (CNTs)
Diameter & V TH
D CNT
=
V th
»
E g
2
q
= 3
a
0 p 3 3
n
2 +
m
2 +
nm a
0 = 0.142
nm aV eD
p
CNT a
» 2.49 ˙
V
p » 3.033
eV
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011
Mean (μ) of V
TH
and K
Device level
• Mean of V th • Mean of V th as T m as N • Mean of K as T m • Mean of K as N
V th
»
E g
2
q
= 3 3
aV
p
eD CNT
CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome , January 17 th -18 th 2011