Transcript EE271 Introduction to VLSI Design

Carbon Nanotube FETs:
Imperfection-Immune Digital VLSI
Subhasish Mitra
H.-S. Philip Wong
Department of EE & Department of CS
Stanford University
BIG Promise, Major Obstacles
Mis-positioned CNTs
Metallic CNTs (m-CNTs)
Imperfection-immune design
essential
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Mis-positioned CNT-Immune NAND
Vdd
1. Grow CNTs
2. Extended gate, contacts
3. Etch gate & CNTs
4. Dope P & N regions

Arbitrary logic functions
A
Out
A
B
Etched
region
essential
B
 Graph algorithms
Gnd
3
Most Importantly

VLSI processing
 No per-unit customization

VLSI design flow
 Immune CNT library
4
m-CNT Processing Options

Grow 0% m-CNTs
 Open challenge

Remove m-CNTs after growth
 99.99%

Early attempts inadequate
 Correctness, scalability
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Solution: VMR

VLSI Metallic CNT Removal
 Universally effective
• All logic designs
 VLSI processing & design flows
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First Wafer-Scale Aligned CNT Growth
Quartz wafer
with catalyst
Aligned
CNT growth
Quartz wafer with CNTs
99.5% aligned CNTs
20mm
Stanford Nanofabrication Facility
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Wafer-Scale CNT Transfer

Low temperature (90oC – 120oC)
Thermal Release
Adhesive Tape
Before transfer
Quartz
After transfer
SiO2/Si
2 µm
2 µm
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First VLSI Demonstration
Mis-positioned CNT-immune
NAND, NOR, AND-OR-INV, OR-AND-INV
Etched Region
10µm
Current (µA)
NAND pullup
100
50
0
A off
B off
off on
on
on off
on
off = 2V, on = -2V
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First Experimental Demonstration
Imperfection-immune CNT VLSI circuits
Arithmetic circuits
Adder Sum
Storage circuits
D-latch
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First Monolithic CNT 3D ICs
3-layer CNFET
inverters
2-layer CNFET
XOR
Conventional via,
NOT TSV
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CNT Variations
m-CNTinduced
Grown
CNT
density
Others:
diameter, doping, channel length
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Overcoming CNT Variations
Energy cost
High
CNT correlation
Unique property
Special
layouts
Co-optimized
processing
Do
Upsize
nothing
Better
process
0%
0%
Yield
High
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Processing & Design Co-Optimization
% grown m-CNTs (pm)
Special layouts
m-CNT removal (pRm, pRs)
CNFET sizing
Grown CNT density variations (IDC)
VMR structure …
Optimized Guidelines
Noise margin
Yield
Delay variations
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Processing & Design Co-Optimization
14%
pm = 10%, IDC = 0.5, pRs = 5%
12%
10%
Delay
penalty
pm = 5%
8%
IDC = 0.25
6%
pRs = 2.5%
4%
2%
Path A: chirality control
pm = 10%  0.1%
Path B: count control
pm = 10%  5%, IDC = 0.5  0.25, pRs = 5%  2.5%
0%
0%
1%
2%
3%
4%
5%
Energy penalty
Example: OpenSPARC T2 “exu” unit at 16nm
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Channel length
scaling
Significant
Experimental
Results
!Recent results: sub-10 nm CNTFET
– SEM and TEM used to determine
channel
length
[1] M.
Li et al., VLSI
Tech. (2009).
Sub-10nm CNFET (IBM)
el length scaling
[2] B. Yu et al., IEDM Tech. Digest p. 251 (2002).
results: sub-10 nm CNTFET
[3] B. Doris et al., IEDM Tech. Digest p. 27.3.1 (2003).
Lch = 9nm
parison with sub-10 nm Si-based FETs with best-reported performance:
Vdd = 0.5V
ric
Gate
Gate
Assume:
Vdd = 0.5
Gate
SSV= 94mV/dec
Dielectric
SiO2 Box
Si Nanowire
Si Fin
! "#
th
is
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f.1
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e
f.2
R
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f.3
ETSOI
|Vds| = 0.5 V
dCNT ~ 1.3nm
|Vgs - Vth| = 0.3 V
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Contributor: A. Franklin (IBM)
Diameter-normalizedPitch
Pitch-normalized
on-currents
normalizedon-currents
A. D. Fr
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Significant Experimental Results
400mV Complementary Inverter (Peking U.)
Gate length = 1mm
Gain = 34
dCNT ~ 1.8nm
CV2 ~ 27pJ
(Projected: 0.5pJ for
20nm gate length)
Single CNT
Contributor: LM Peng (Peking U.)
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Significant Experimental Results
Increased CNT Density
Target: 100 – 200 CNTs / mm
1. Growth / transfer:  Good alignment,  density variations challenging
CNT multiple transfer: (Stanford)
a
b
1X
4X
2X
2µm
2µm
Recent News:
100 CNTs / mm
2µm
c
Source 1
CNTs
Source 2
Ÿ
Ÿ
Ÿ
(Rogers, UIUC, in press)
Target Substrate
Source N
N Independent CNT Sources
(a)
(b)
CNTs CNT spacing
CNT Count distribution
CNT Spacing distribution
0.1
Width = 2 µm
W
Probability
L
Probability
2. Dispersed from solution: Great recent progress (IBM, unpublished)
0.2
0.1
0.08
0.06
0.04
Up to 10 CNTs / mm, good alignment, consistent pitch
0.02
0
CNFET: W / L
5
10
15
20
25
CNT count per CNFET
0
0
0.4
0.8
1.2
1.6
Spacing (µm)
(d)
(c)
(e)
Contributors: W. Haensch
(IBM),
J. Rogers (UIUC)
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Significant Experimental Results
Semiconducting CNTs (s-CNTs)
Target: s-CNTs > 99.9999%
1. (In-place) m-CNT removal:  99.99% removed,  CNT count variations
VMR (Stanford)
Rogers, UIUC
99.99% m-CNTs, 5% s-CNTs removed
Alternative to electrical
breakdown
(in press)
m-CNT electrical breakdown
2. Sort & place: Great recent progress (IBM, unpublished)
99.4% s-CNTs
Contributors: W. Haensch (IBM), J. Rogers (UIUC)
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Significant Experimental Results
Imperfection-immune VLSI (Stanford)
Adder
D-latch
Wafer-scale VLSI integration
Yield: CNFETs (99%), …
Issues explainable: non-ideal litho, …
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Summary

Significant CNFET progress

Imperfection-immune design essential
 New solutions: elegantly simple, practical

Next challenge
 Energy-efficient CNFET digital systems
More details: NIST CNFET workshop report (Sept. 6, 2012)
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Next Steps

CNT material
 High density, minimize m-CNTs
• Quickly quantify purity

Device
 Doping: n/p, stable, controllable
 Low contact resistance
 Thin gate dielectrics, passivation (hysteresis)
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Next Steps

Design
 Variability
• Quantify, overcome
• Unique CNT properties (e.g., correlation)
 Material, device, design co-optimization
 Monolithic 3D: new opportunity ?
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