Transcript Synopsys model

Synopsys model
溫家聖
Outline
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Design methodologies
Synopsys model
LEF_Abstract & Modify LEF file
SOC encounter
Stream in & Verification
Homework
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Outline
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Design methodologies
Synopsys model
LEF_Abstract & Modify LEF file
SOC encounter
Stream in & Verification
Homework
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Design methodologies
• Full-custom
– Starting from transistor circuits
• Application Specific Integrated Circuits(ASIC)
– Starting from HDL with support of standard cell library
and
logic synthesis tools
– Cell-based design flow
• FPGA
– Starting from HDL with support of FPGA synthesis
tools
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Design Flow
Specification
• Left fork
– Full custom
• Center fork
– ASIC
Architecture
Functional
Description
Functional
Description
Circuit
Design
Logic
Synthesis
Layout
Auto Layout
Generation
Purchase
Components
• Right fork
– System on Chip
Chip
Assembly
Physical
Verification
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Full custom design flow
• Give the designer the most freedom
– Lots of rope
• Can be clever
• Can huge yourselves too
• For a specific function
– Can achieve best performance
• Speed , power, area, etc
– Most work/time per function
– Optimizations are at a low level
• Circuit better be important
• Think assembler, only worse
Device Circuit
Topology
Size Transistors
Simulation
Layout
Design Rule
Check (DRC)
Layout vs.
Schematic(LVS)
Parasitic
Extraction(LPE)
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ASIC cell-based design flow
Specification
• Separate teams to
design and verify
• Physical design is
(semi-) automated
• Loops to get device
operating frequency
correct can be troubling
Functional
Description(RTL)
Function
Verification
english
Testbench and
Vectors
verilog
vhdl
Logic Synthesis
Static Timing
Design compiler(Synopsys)
Primetime(Synopsys)
Place and Route
Silicon Ensemble(Cadence)
DRC
LVS
LPE
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Outline
•
•
•
•
•
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Design methodologies
Synopsys model
LEF_Abstract & Modify LEF file
SOC encounter
Stream in & Verification
Homework
9
Synopsys model
• 在cell-based設計流程下，使用Synopsys DC
搭配自建元件合成電路
– 所需模組：提供library檔案(*.lib)，利用
SYNOPSYS的library compiler編譯成db檔，載入
*.db檔便可以合成
編輯synopsys model
Synopsys
(將synopsys model編輯成文字檔)
(產生database file)
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建立synopsys model for each cells
• 我們可以建立cell之synopsys model，讓
sysnopsys 來合成我們所設計的電路，而如
果要使用synopsys 來synthesis circuit ，則至
少必須有三種cell ，inverter ， nor 和nand，
如果要合成序向電路則還需要DFF元件(需含
有reset訊號腳位)
• 基本參數的設定：
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>> gedit my_lib &
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INV範例
Delay
Cload=0.64
斜率為resistance
intrinsic
Cload=0.04
Cload
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NOR範例
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下一步
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>> dv &
執行synopsys
• 建立好Synopsys後開dv在Command Window下執行
Synosys model
1. read_lib my_lib.lib
name
Library name
2. write_lib my_lib
元件庫名稱
成功後關掉
Command Window
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環境設定檔–指令:
gedit .synopsys_dc.setup &
• 作synopsys設定，檔案中設定的項目下所述 :
– link_library : 解譯input 檔案敘述所使用的library
– target_library : Design 所map 到的ASIC technology
– symbol_library : 產生schematic 所需要用到的各種
symbol view
– search_path : 搜尋未定義的reference library 的路徑
– synthetic_library : 指定designware library
– 其他Synopsys 所定義的變數設定
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>> ~/.synopsys_dc.setup &
範例檔案
• 我們所建立的cell library 的名字為my_lib.db
所其環境設定如下：
如果我的的library 放在根目錄下
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>> dv &
Step1.啟動Synopsys
• Filesetup，作確認的動作
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Step2.讀入Design
• FileRead ，將要作合成的*.v檔讀入
當檔案讀入時，會出現如果有error 或warning 之訊息,
會show 在此訊息框。
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Step3.合成
• DesignCompile DesignOK
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Step4.確認是否有用到自建的元件
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Step4.確認是否有用到自建的元件
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Step5.合成結果分析(Area)
• DesignReport AreaOK
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Step5.合成結果分析(Area)
這裡的單位：gate count，
因為之前元件庫裡的單位為gate count
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Step5.合成結果分析(Delay
information)
• TimingReport Timing PathOK
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Step5.合成結果分析(Delay
information)
critical path
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Step6.將合成後的結果存下(gatelevel
檔)
• FileSave as*.gv/*.v檔
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