Transcript Lecture 11 - VHDL Coding for Synthesis. Algorithmic State Machines.

ECE 448
Lecture 11
VHDL Coding for Synthesis
Algorithmic State Machines
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Required reading
• S. Lee, Advanced Digital Logic Design,
Chapter 3.3, More Advanced VHDL Concepts
(handout)
• S. Brown and Z. Vranesic, Fundamentals of Digital
Logic with VHDL Design
Chapter 8.10, Algorithmic State Machine
(ASM) Charts
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Variables vs. Signals (1)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY test_delay IS
PORT(
clk : IN STD_LOGIC;
in1, in2 : IN STD_LOGIC;
var1_out, var2_out : OUT STD_LOGIC;
sig1_out : BUFFER STD_LOGIC;
sig2_out : OUT STD_LOGIC
);
END test_delay;
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Variables vs. Signals (2)
ARCHITECTURE behavioral OF test_delay IS
BEGIN
PROCESS(clk) IS
VARIABLE var1, var2: STD_LOGIC;
BEGIN
if (rising_edge(clk)) THEN
var1 := in1 AND in2;
var2 := var1;
sig1_out <= in1 AND in2;
sig2_out <= sig1_out;
END IF;
var1_out <= var1;
var2_out <= var2;
END PROCESS;
END behavioral;
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Simulation result
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Sequential Logic Synthesis
for
Advanced
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Sequence detector (for 0111_1110)
Step 1. prev_data = 1111_1111
Step 2. while(TRUE) do /* repeat forever */
data_in = next data input;
prev_data = prev_data << 1;
prev_data(0) = data_in;
if (prev_data == 0111_1110) then
detected = 1
else
detected = 0
end while;
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Sequence Detector – Entity declaration
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY seq_det_1 IS
PORT(
reset_n : IN STD_LOGIC;
clk : IN STD_LOGIC;
data_in : IN STD_LOGIC;
detected : OUT STD_LOGIC
);
END seq_det_1;
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Architecture 1 with variables & SLL
LIBRARY IEEE;
USE IEEE.NUMERIC_STD.all;
ARCHITECTURE behavioral_1 OF seq_det_1 IS
BEGIN
PROCESS(reset_n, clk)
VARIABLE prev_data: UNSIGNED(7 DOWNTO 0);
BEGIN
IF (reset_n = '0') THEN
prev_data := B"1111_1111";
ELSIF rising_edge(clk) THEN
prev_data := prev_data SLL 1;
prev_data(0) := data_in;
IF (prev_data = B"0111_1110") THEN
detected <= '1';
ELSE
detected <= '0';
END IF;
END IF;
END PROCESS;
END behavioral_1;
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Architecture 2 with variables
ARCHITECTURE behavioral_2 OF seq_det_1 IS
BEGIN
PROCESS(reset_n, clk)
VARIABLE prev_data: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF (reset_n = '0') THEN
prev_data := B"1111_1111";
ELSIF rising_edge(clk) THEN
prev_data := prev_data(6 downto 0) & data_in;
IF (prev_data = B"0111_1110") THEN
detected <= '1';
ELSE
detected <= '0';
END IF;
END IF;
END PROCESS;
END behavioral_2;
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Architecture 3 with signals
ARCHITECTURE behavioral_3 OF seq_det_1 IS
SIGNAL prev_data: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(reset_n, clk)
BEGIN
IF (reset_n = '0') THEN
prev_data <= B"1111_1111";
ELSIF rising_edge(clk) THEN
prev_data <= prev_data(6 downto 0) & data_in;
IF (prev_data(6 downto 0) & data_in = B"0111_1110") THEN
detected <= '1';
ELSE
detected <= '0';
END IF;
END IF;
END PROCESS;
END behavioral_3;
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Synthesised circuit
data_in
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Algorithmic State Machine (ASM)
Charts
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Algorithmic State Machine
Algorithmic State Machine –
representation of a Finite State Machine
suitable for FSMs with a larger number of
inputs and outputs compared to FSMs
expressed using state diagrams and state
tables.
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Elements used in ASM charts (1)
State name
Output signals
or actions
(Moore type)
0 (False)
(a) State box
Condition
expression
1 (True)
(b) Decision box
Conditional outputs
or actions (Mealy type)
(c) Conditional output box
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Elements used in ASM charts (2)
• State box – represents a state.
Equivalent to a node in a state diagram or a row
in a state table.
Moore type outputs are listed inside of the box. It
is customary to write only the name of the signal
that has to be asserted in the given state, e.g., z
instead of z=1. Also, it might be useful to write an
action to be taken, e.g., Count = Count + 1, and
only later translate it to asserting a control signal
that causes a given action to take place.
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Elements used in ASM charts (3)
• Decision box – indicates that a given condition is
to be tested and the exit path is to be chosen
accordingly
The condition expression consists of one or more
inputs to the FSM.
• Conditional output box – denotes output
signals that are of the Mealy type.
The condition that determines whether such
outputs are generated is specified in the decision
box.
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Moore FSM – Example 1: State diagram
Reset
w = 1
w = 0
A z = 0
B z = 0
w = 0
w = 1
w = 0
C z = 1
w = 1
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ASM Chart for Moore FSM – Example 1
Reset
A
0
w
1
B
0
w
1
C
z
0
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w
1
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Example 1: VHDL code (1)
USE ieee.std_logic_1164.all ;
ENTITY simple IS
PORT ( clock
resetn
w
z
END simple ;
: IN STD_LOGIC ;
: IN STD_LOGIC ;
: IN STD_LOGIC ;
: OUT STD_LOGIC ) ;
ARCHITECTURE Behavior OF simple IS
TYPE State_type IS (A, B, C) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( resetn, clock )
BEGIN
IF resetn = '0' THEN
y <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
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Example 1: VHDL code (2)
CASE y IS
WHEN A =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN
y <= A ;
ELSE
y <= C ;
END IF ;
WHEN C =>
IF w = '0' THEN
y <= A ;
ELSE
y <= C ;
END IF ;
END CASE ;
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Example 1: VHDL code (3)
END IF ;
END PROCESS ;
z <= '1' WHEN y = C ELSE '0' ;
END Behavior ;
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Mealy FSM – Example 2: State diagram
Reset
w = 1 z = 0
w = 0 z = 0
A
B
w = 1 z = 1
w = 0 z = 0
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ASM Chart for Mealy FSM – Example 2
Reset
A
0
w
1
B
z
0
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w
1
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Example 2: VHDL code (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Mealy IS
PORT ( clock : IN
resetn : IN
w
: IN
z
: OUT
END Mealy ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ;
STD_LOGIC ) ;
ARCHITECTURE Behavior OF Mealy IS
TYPE State_type IS (A, B) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( resetn, clock )
BEGIN
IF resetn = '0' THEN
y <= A ;
ELSIF (clock'EVENT AND clock = '1') THEN
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Example 2: VHDL code (2)
CASE y IS
WHEN A =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN
y <= A ;
ELSE
y <= B ;
END IF ;
END CASE ;
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Example 2: VHDL code (3)
END IF ;
END PROCESS ;
z <= '1' WHEN (y = B) AND (w=‘1’) ELSE '0' ;
END Behavior ;
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Control Unit Example: Arbiter (1)
reset
g1
r1
r2
Arbiter
g2
g3
r3
clock
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Control Unit Example: Arbiter (2)
000
Reset
Idle
0xx
1xx
gnt1 g1 = 1
x0x
1xx
01x
gnt2 g2 = 1
xx0
x1x
001
gnt3 g3 = 1
xx1
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Control Unit Example: Arbiter (3)
r 1r 2 r 3
Reset
Idle
r1
r1
gnt1 g1 = 1
r1
r2
r 1r 2
gnt2 g2 = 1
r2
r3
r 1r 2 r 3
gnt3 g3 = 1
r3
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ASM Chart for Control Unit - Example 3
Reset
Idle
r1
1
gnt1
0
1
g1
r2
1
gnt2
g2
r3
0
1
0
0
r1
r2
0
1
1
gnt3
g3
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0
r3
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Example 3: VHDL code (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY arbiter IS
PORT ( Clock, Resetn
r
g
END arbiter ;
: IN
: IN
: OUT
STD_LOGIC ;
STD_LOGIC_VECTOR(1 TO 3) ;
STD_LOGIC_VECTOR(1 TO 3) ) ;
ARCHITECTURE Behavior OF arbiter IS
TYPE State_type IS (Idle, gnt1, gnt2, gnt3) ;
SIGNAL y : State_type ;
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Example 3: VHDL code (2)
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN y <= Idle ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN Idle =>
IF r(1) = '1' THEN y <= gnt1 ;
ELSIF r(2) = '1' THEN y <= gnt2 ;
ELSIF r(3) = '1' THEN y <= gnt3 ;
ELSE y <= Idle ;
END IF ;
WHEN gnt1 =>
IF r(1) = '1' THEN y <= gnt1 ;
ELSE y <= Idle ;
END IF ;
WHEN gnt2 =>
IF r(2) = '1' THEN y <= gnt2 ;
ELSE y <= Idle ;
END IF ;
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Example 3: VHDL code (3)
WHEN gnt3 =>
IF r(3) = '1' THEN y <= gnt3 ;
ELSE y <= Idle ;
END IF ;
END CASE ;
END IF ;
END PROCESS ;
g(1) <= '1' WHEN y = gnt1 ELSE '0' ;
g(2) <= '1' WHEN y = gnt2 ELSE '0' ;
g(3) <= '1' WHEN y = gnt3 ELSE '0' ;
END Behavior ;
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