Transcript FINITE STATE MACHINES

FINITE STATE MACHINES - II

STATE MINIMIZATION



ANALYSIS OF SYNCHRONOUS SEQUENTIAL
CIRCUITS




PARTITIONING MINIMIZATION PROCEDURE
VENDING MACHINE EXAMPLE
PROCEDURE
EXAMPLE
ALGORITHMIC STATE MACHINES (ASM) CHARTS
COMPLETE FSM DESIGN EXAMPLE
PARALLEL-TO-SERIAL CONVERTER WITH PARITY
GENERATOR
__________________________________________________

ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II
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STATE MINIMIZATION
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PARTITIONING MINIMIZATION PROCEDURE
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DEFINITION: Two states Si and Sj are said to be equivalent if and only
if for every input sequence , the same output sequence will be
produced regardless of whether Si or Sj are the initial states.
DEFINITION OF 1-SUCCESSOR : If the machine moves from state Si to
state Sv when input w = 1, then we say that Sv is a 1-successor of Si
DEFINITION OF 0-SUCCESSOR : If the machine moves from state Sj to
state Su when input w = 0, then we say that Su is a 0-successor of Si
IF STATES Si AND Sj ARE EQUIVALENT, THEN THEIR
CORRESPONDING K-SUCCESSORS (FOR ALL K) ARE ALSO
EQUIVALENT.
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II
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STATE MINIMIZATION
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PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
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DEFINITION: A PARTITION CONSISTS OF ONE OR MORE
BLOCKS, WHERE EACH BLOCK COMPRISES A SUBSET OF
STATES THAT MAY BE EQUIVALENT, BUT THE STATES IN A
GIVEN BLOCK ARE DEFINITELY NOT EQUVALENT TO THE
STATES IN THE OTHER BLOCK.
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II
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STATE MINIMIZATION
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PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
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PROCEDURE:
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1) ALL STATES BELONG TO THE INITIAL PARTITION P1
2) P1 IS PARTITIONED IN BLOCKS SUCH THAT THE STATES IN
EACH BLOCK GENERATE THE SAME OUTPUT.
3) CONTINUE TO PERFORM NEW PARTITIONS BY TESTING
WHETHER THE K-SUCCESSORS OF THE STATES IN EACH
BLOCK ARE CONTAINED IN ONE BLOCK. THOSE STATES
WHOSE K-SUCCESSORS ARE IN DIFFERENT BLOCKS CANNOT
BE IN ONE BLOCK.
4) PRCEDURE ENDS WHEN A NEW PARTITION IS THE SAME AS
.THE PREVIOUS PARTITION
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FINITE STATE MACHINES - II
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STATE MINIMIZATION
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PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
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EXAMPLE: Consider the following state transition table
Next state
Present
state
w= 0
w= 1
Output
z
A
B
C
D
E
F
G
B
D
F
B
F
E
F
C
F
E
G
C
D
G
1
1
0
1
0
0
0
P1 = (ABCDEFG)
P2 = (ABD)(CEFG) Diff. Outputs.
Because (CEFG) 0-successors are (FFEF) in
same block,
(CEFG) 1-successors are (ECDG)
in diff. block,
F must be different from C, E and G
P3 = (ABD)(CEG)(F)
P4 = (AD)(B)(CEG)(F)
Same process for (AD) and (CEG) gives
P5 = (AD)(B)(CEG)(F)
P5 = P4
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FINITE STATE MACHINES - II
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STATE MINIMIZATION
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PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
EXAMPLE (CONTINUES): MINIMAL STATE TRAMSITION TABLE
ORIGINAL TABLE
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Present
state
A
B
C
D
E
F
G
Next state
w= 0
w= 1
Output
z
B
D
F
B
F
E
F
C
F
E
G
C
D
G
1
1
0
1
0
0
0
P4 = (AD)(B)(CEG)(F)
MINIMIZED TABLE
Nextstate
Present
state
w= 0
w= 1
Output
z
A
B
C
F
B
A
F
C
C
F
C
A
1
1
0
0
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FINITE STATE MACHINES - II
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STATE MINIMIZATION
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VENDING MACHINE EXAMPLE
Design an FSM that will dispense candy under the following
conditions:
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1.2.3.-
The machine accepts nickels and dimes
15 cents releases a candy from the machine
If 20 cents is deposited, the machine will not return the
change, but it credit the buyer with 5 cents and wait for
the buyer to make a second purchase
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ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II
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STATE MINIMIZATION
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VENDING MACHINE EXAMPLE (Continues)
Clock
sense
N
sense
D
N
D
(a) Timing diagram
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II
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STATE MINIMIZATION
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VENDING MACHINE EXAMPLE (Continues)
N
sense
N
Clock
D
Q
Q
D
Q
Q
(b) Circuit that generates N
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II
STATE MINIMIZATION: VENDING MACHINE EXAMPLE (Continues)
DN
Reset
DN
S10
DN
DN
DN
DN
D
S41
N
N
S20
S30
D
N
DN
S60
S51
N
D
S71
DN
DN
D
S81
S91
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II
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STATE MINIMIZATION
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VENDING MACHINE EXAMPLE (Continues)
Next state
Present
Output
state DN =00 01 10 11
z
P1 = (S1, S2, S3, S4, S5, S6, S7, S8, S9)
P2 = (S1, S2, S3, S6)(S4, S5, S7, S8, S9)
P3 = (S1)(S3)(S2, S6)(S4, S5, S7, S8, S9)
P4 = (S1)(S3)(S2, S6)(S4, S7, S8)(S5,S9)
P5 = (S1)(S3)(S2, S6)(S4, S7, S8)(S5,S9)
S1
S1 S3 S2 –
0
S2
S2 S4 S5 –
0
S3
S3 S6 S7 –
0
S4
S1 – – –
1
S5
S3 – – –
1
S6
S6 S8 S9 –
0
S7
S1 – – –
1
S8
S1 – – –
1
S9
S3 – – –
1
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II
STATE MINIMIZATION: VENDING MACHINE EXAMPLE (Continues)
DN
MINIMIZED STATE TRANSITION TABLE AND DIAGRAM
S10
Next state
Present
Output
state DN =00 01 10 11
z
S1
S2
S3
S4
S5
S1
S2
S3
S1
S3
S3 S2
S4 S5
S2 S4
– –
– –
–
–
–
–
–
0
0
0
1
1
N
DN
D
DN
S30
DN
N
DN
S20
D
S51
N
D
S41
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FINITE STATE MACHINES - II
STATE MINIMIZATION: VENDING MACHINE EXAMPLE (Continues)
MINIMIZED STATE TRANSITION DIAGRAM: Moore-type versus Mealy-type
DN0
DN
MOORE-TYPE
MEALY_TYPE
S10
DN
N0
N
DN
D
S1
DN0
S30
N1
DN
N
DN
S20
D1
D
S51
D0
S3
N0
D1
S2
N
D
S41
DN0
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FINITE STATE MACHINES - II

ANALYSIS OF SYNCHRONOUS SEQUENTIAL
CIRCUITS
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PROCEDURE: is the reverse of the synthesis process.
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1.- OUTPUTS OF FLIP-FLOPS ARE THE INTERNAL STATES.
2.- INPUT EQUATIONS TO FLIP-FLOPS DETERMINE NEXT INTERNAL
STATE.
3.- EXCITATION TABLE IS CONSTRUCTED FROM THESE INPUT
EQUATIONS TO FLIP-FLOPS. OUTPUT EQUATIONS ARE PRODUCED.
4.- THE STATE-ASSIGNED TABLE IS PRODUCED FROM THE EXCITATION TABLE
5.- THE STATE-TRANSITION TABLE IS PRODUCED BY ASSIGNING A STATE
IDENTIFICATION LETTER TO EACH ASSIGNED STATE.
6.- THE STATE-TRANSITION DIAGRAM IS PRODUCED FROM THE STATETRANSITION TABLE.
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II
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ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
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EXAMPLE: ANALYZE THE FOLLOWING CIRCUIT
Y1
D
Q
y1
Q
w
Y2
D
Clock
Q
y2
Exitation equations: DY1 = w !y1 + w y2
DY2 = w y1 + w y2
z
z = y1 y2
Next state equations:
Y1 = DY1 = w !y1 + w y2
Y2 = DY2 = w y1 + w y2
Q
Resetn
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II

ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
EXAMPLE (Continues)
Exitation equations:
DY1 = w !y1 + wy2
DY2= w y1 + w y2
z = y1 y2
Next state equations:
Y1 = DY1 = w !y1 + w y2
Y2 = DY2 = w y1 + w y2
Present
state
2 1
y y
00
01
10
11
Next State
Output
w= 0
w= 1
YY
YY
2 1
z
00
00
00
00
01
10
11
11
0
0
0
1
2 1
(a) State-assigned table
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II

ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
EXAMPLE (Continues)
Present
state
2 1
y y
00
01
10
11
Next State
Output
w= 0
w= 1
YY
YY
2 1
z
00
00
00
00
01
10
11
11
0
0
0
1
2 1
Present
state
A
B
C
D
Next state
Output
w= 0
w= 1
z
A
A
A
A
B
C
D
D
0
0
0
1
(b) State table
(a) State-assigned table
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II

ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
ANOTHER EXAMPLE: Analyze the following circuit
J1
w
K1
J2
J
Q
K
Q
J
Q
K
Q
y1
z
y2
Clock
K2
Resetn
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II
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w
ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
ANOTHER EXAMPLE (Continues)
y1
J1
Excitation Equations
J Q
z
J1 = w
K Q
K1
K1 = !w + !y2
J2 = w y1
K2 = !w
J2
J
Q
y2
z = y1 y2
Clock
K2
K Q
Resetn
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II

ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
ANOTHER EXAMPLE (Continues)
Excitation Equations
J1 = w
Flip-flop inputs
K1 = !w + !y2
Present
J2 = w y1
state
w= 0
w= 1
K2 = !w
y2 y1
J 2K 2 J 1K 1 J 2K 2 J 1K 1
z = y1 y2
Output
z
00
01
01
00
11
0
01
01
01
10
11
0
10
01
01
00
10
0
11
01
01
10
10
1
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II

ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS ANOTHER EXAMPLE
(Continues)
EXCITATION TABLE
STATE-ASSIGNED TABLE
Present
state
y2y1
Flip-flop inputs
w= 0
J 2K 2
J 1K 1
w= 1
J 2K 2
J 1K 1
Output
z
Present
state
2 1
y y
Next State
Output
w= 0
2 1
YY
w= 1
2 1
YY
z
00
01
01
00
11
0
00
00
01
0
01
01
01
10
11
0
01
00
10
0
10
00
11
0
10
01
01
00
10
0
11
00
11
1
11
01
01
10
10
1
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II

ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
EXAMPLE (Continues)
Present
state
2 1
y y
00
01
10
11
Next State
Output
w= 0
w= 1
YY
YY
2 1
z
00
00
00
00
01
10
11
11
0
0
0
1
2 1
Present
state
A
B
C
D
Next state
Output
w= 0
w= 1
z
A
A
A
A
B
C
D
D
0
0
0
1
(b) State table
(a) State-assigned table
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II

ALGORITHMIC STATE MACHINES (ASM) CHARTS

DEFINITION: An ASM is a type of flowchart that can be used to represent
the state transitions and generated outputs for LARGE FSMs.
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THREE TYPES OF ELEMENTS:
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STATE BOX, DECISION BOX, CONDITIONAL OUTPUT BOX.
State name
Output signals
or actions
(Moore type)
(a) State box
0 (False)
Condition
expression
1 (True)
Conditional outputs
or actions (Mealy type)
(c) Conditional output box
__________________________________________________
(b) Decision box
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II
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ALGORITHMIC STATE MACHINES (ASM) CHARTS (Continues)
Reset
Example: Moore-type
Reset
A
w=0
A z = 0
w=1
B z = 0
w=0
0
C z = 1
1
B
w=1
w=0
w
0
w=1
w
1
C
z
0
1
w
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II
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ALGORITHMIC STATE MACHINES (ASM) CHARTS (Continues)
Reset
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EXAMPLE (Mealy-type)
A
Reset
w = 1 z = 0
0
w = 0z = 0
B
A
w
w = 1 z = 1
1
w = 0 z = 0
B
z
0
w
1
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II
ALGORITHMIC STATE MACHINES (ASM) CHARTS (Continues)
ANOTHER EXAMPLE (ARBITER MOORE-TYPE FSM): FSM THAT CONTROLS THE ACCESS BY VARIOUS DEVICES TO A SHARED
RESOURCE IN A GIVEN SYSTEM. ONLY ONE DEVICE CAN USE THE RESOURCE AT A TIME.
Reset
r 1r 2 r 3
Reset
Idle
Idle
r1
r1
1
gnt1
0
r2
0
r2
g2
r2
0
1
g3
r3
r 1r 2
r3
r2
r 1r 2 r 3
gnt3 g3 = 1
1
gnt3
r1
gnt2 g2 = 1
1
gnt2
r3
r1
1
0
0
gnt1 g1 = 1
1
g1
r1
0
r3
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FINITE STATE MACHINES - II

COMPLETE FSM DESIGN EXAMPLE
PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR

Word description

Design a digital systems that will convert an 8-bit parallel
message, (b7 , b6 , b5 , b4 , b3 , b2 , b1 , b0), composed
of 7-bit ASCII character plus an initially set to 0 parity
bit, into an 8-bit serial message with the correct parity
bit set into bit b7 .
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II

COMPLETE FSM DESIGN EXAMPLE
PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR

BLOCK DIAGRAM (Data Path and Control Unit)
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II

COMPLETE FSM DESIGN EXAMPLE
PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR

STATE TRANSITION TABLE
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II

COMPLETE FSM DESIGN EXAMPLE
PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR
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STATE-ASSIGNED TABLE
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CHOICE OF FLIP-FLOPS AND EXCITATION EQUATION
Dy = Y = w  y
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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FINITE STATE MACHINES - II

COMPLETE FSM DESIGN EXAMPLE
PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR

CIRCUIT
__________________________________________________
ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin.
Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2 nd Edition, McGraw Hill.
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