Transcript PPT - ECE/CS 352 On

ECE/CS 352: Digital Systems Fundamentals
Lecture 20 – Analyzing
Sequential Logic
Charles Kime & Thomas Kaminski
© 2004 Pearson Education, Inc.
Terms of Use
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Overview
 Finite State Machine Model
 State Tables
 State Diagrams
 Moore and Mealy Models
 Circuit and System Level Timing
Chapter 6 - Part 1
2
Finite State Machine Model
 General Model
Inputs
Outputs
• Current State
Combinaat time (t) is
tional
Logic
stored in an Storage
Elements
array of
Next
flip-flops.
State
State
• Next State at time (t+1)
is a Boolean function of CLK
State and Inputs.
• Outputs at time (t) are a Boolean function of
State (t) and (sometimes) Inputs (t).
Chapter 6 - Part 1
3
Example 1 (from Fig. 6-17)




Input:
x(t)
x
Output: y(t)
State:
(A(t), B(t))
What is the Output
Function?
y(t )  ( A(t )  B(t ))X (t )
 What is the Next State
Function?
Q
A
C Q
A
Q
B
D
D
CP
C Q
y
A(t  1)  A(t ) x(t )  B(t ) x(t )
B(t  1)  A(t )x(t )
Chapter 6 - Part 1
4
Example 1 (continued)
 Where in time are inputs, outputs and
states defined?
1
0
1
0
0
0
1
0
Chapter 6 - Part 1
5
Example 1: State Table
 The state table can be filled in using the next state and
output equations:
A(t  1)  A(t ) x(t )  B(t ) x(t ) y(t )  ( A(t )  B(t ))X (t )
B(t  1)  A(t )x(t )
Present State Input
A(t)
0
0
0
0
1
1
1
1
B(t)
0
0
1
1
0
0
1
1
x(t)
0
1
0
1
0
1
0
1
Next State Output
A(t+1) B(t+1)
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
0
y(t)
0
0
1
0
1
0
1
0
Chapter 6 - Part 1
6
Example 1: Alternate State Table
 2-dimensional table that matches well to a K-map.
Present state rows and input columns in Gray code
order.
• A(t+1) = A(t)x(t) + B(t)x(t)
• B(t+1) =A (t)x(t)
• y(t) =x (t)(B(t) + A(t))
Present
Next State
Output
State
x(t)=0
x(t)=1
x(t)=0 x(t)=1
A(t) B(t) A(t+1)B(t+1) A(t+1)B(t+1) y(t) y(t)
0 0
0 0
0 1
0
0
0 1
0 0
1 1
1
0
1 1
0 0
1 0
1
0
1 0
0 0
1 0
1
0
Chapter 6 - Part 1
7
State Diagrams
x=0/y=0
 Graphical
specification
 Nodes  states x=1/y=0
 Edges  transitions
x=0/y=1
AB
00
x=0/y=1 1 0
x=1/y=0
• Depend on inputs
x=0/y=1
 Outputs
• Based on state
• Based on state and
input
x=1/y=0
11
01
x=1/y=0
Chapter 6 - Part 1
8
Moore and Mealy Models
 Finite State Machines (FSMs) have two
formal models:
 Moore Model
• Named after E.F. Moore.
• Outputs are a function
ONLY of states
• Usually specified on the
states.
 Mealy Model
• Named after G. Mealy
• Outputs are a function of
inputs AND states
• Usually specified on the
state transition arcs.
 In contemporary design, models are
sometimes mixed Moore and Mealy
Chapter 6 - Part 1
9
Moore and Mealy Example Diagrams
 Mealy Model State Diagram
maps inputs and state to outputs
x=0/y=0
x=1/y=0
1
0
 Moore Model State Diagram x=0
maps states to outputs
x=0/y=0
0/0
x=1/y=1
x=0
x=1
x=1
x=0
1/0
2/1
x=1
Chapter 6 - Part 1
10
Moore and Mealy Example Tables
 Mealy Model state table maps inputs and
state to outputs
Present
State
0
1
Next State
x=0 x=1
0
1
0
1
Output
x=0 x=1
0
0
0
1
 Moore Model state table maps state to
Present Next State Output
outputs
State
0
1
2
x=0 x=1
0
1
0
2
0
2
0
0
1
Chapter 6 - Part 1
11
Sequential Circuit Analysis Example
 Logic Diagram:
D
Q
A
Z
C RQ
D
Q
B
C RQ
D
Clock
Reset
Q
C
CR Q
Chapter 6 - Part 1
12
Example 2: Flip-Flop Input Equations
 Variables
• Inputs: None
• Outputs: Z
• State Variables: A, B, C
 Initialization: Reset to (0,0,0)
 Equations:
A(t  1)  BC
B(t  1)  BC  BC
C (t  1)  AC
ZA
Chapter 6 - Part 1
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Example 2: State Table
X’ = X(t+1)
A'  BC
B '  BC  BC
C '  AC
ZA
ABC
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A’B’C’
0 0 1
0 1 0
0 1 1
1 0 0
0 0 0
0 1 0
0 1 0
1 0 0
Z
0
0
0
0
1
1
1
1
Chapter 6 - Part 1
14
Example 2: State Diagram
Reset
111
ABC
000
100
001
011
010
 Which states are used?
 What is the function of
the circuit?
101
110
Chapter 6 - Part 1
15
Circuit and System Level Timing
 Consider a system
comprised of ranks
of flip-flops
connected by logic:
 If the clock period is
too short, some
data changes will not
propagate through the
circuit to flip-flop
inputs before the setup
time interval begins
D Q
D Q
C Q'
C Q'
D Q
D Q
C Q'
C Q'
D Q
D Q
C Q'
C Q'
D Q
D Q
C Q'
C Q'
D Q
D Q
C Q'
C Q'
CLOCK
CLOCK
Chapter 6 - Part 1
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Circuit and System Level Timing
(continued)
 Timing components along a path from flip-flop
to flip-flop
tp
C
tpd,FF
tpd,COMB
ts
tslack
(a) Edge-triggered (positive edge)
tp
C
tpd,FF
tpd,COMB
tslack
ts
(b) Pulse-triggered (negative pulse)
Chapter 6 - Part 1
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Circuit and System Level Timing
(continued)
 New Timing Components
• tp - clock period - The interval between occurrences
of a specific clock edge in a periodic clock
• tpd,COMB - total delay of combinational logic along the
path from flip-flop output to flip-flop input
• tslack - extra time in the clock period in addition to
the sum of the delays and setup time on a path
 Can be either positive or negative
 Must be greater than or equal to zero on all paths for
correct operation
Chapter 6 - Part 1
18
Circuit and System Level Timing
(continued)
 Timing Equations
tp = tslack + (tpd,FF + tpd,COMB + ts)
• For tslack greater than or equal to zero,
tp ≥ max (tpd,FF + tpd,COMB + ts)
for all paths from flip-flop output to flip-flop input
 Can be calculated more precisely by using tPHL
and tPLH values instead of tpd values, but
requires consideration of inversions on paths
Chapter 6 - Part 1
19
Calculation of Allowable tpd,COMB
 Compare the allowable combinational delay for a
specific circuit:
a) Using edge-triggered flip-flops
b) Using master-slave flip-flops
 Parameters
•
•
•
•
tpd,FF(max) = 1.0 ns
ts(max) = 0.3 ns for edge-triggered flip-flops
ts = twH = 1.0 ns for master-slave flip-flops
Clock frequency = 250 MHz
Chapter 6 - Part 1
20
Calculation of Allowable tpd,COMB
(continued)
 Calculations: tp = 1/clock frequency = 4.0 ns
• Edge-triggered: 4.0 ≥ 1.0 + tpd,COMB + 0.3
→ tpd,COMB ≤ 2.7 ns
• Master-slave: 4.0 ≥ 1.0 + tpd,COMB + 1.0
→ tpd,COMB ≤ 2.0 ns
 Comparison: Assume average gate tpd = 0.3 ns
• Edge-triggered: Approximately 9 gates allowed on a path
• Master-slave: Approximately 6 to 7 gates allowed on a path
Chapter 6 - Part 1
21
Summary
 Finite State Machine Model
 State Tables
 State Diagrams
 Moore and Mealy Models
 Circuit and System Level Timing
Chapter 6 - Part 1
22
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Chapter 6 - Part 1
23