Transcript Coverage Driven Verification for Analog Design Based on UCIS

Coverage Driven Verification for
Analog Design Based on UCIS
Atul Pandey
Guido Clemens
Marius Sida
Mentor Graphics Deutschland Gmbh
Arnulfstr 201, Munich, Germany – 80634
Design Process : Birds Eye View
Analog and Digital design process
are “similar” and follow same
phases
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Digital Design and Verification Process
TestPlan
Merged
coverage db
Product/IP
specification
entity oqpsk_modulator
port (
signal chip_I
: in
signal chip_Q
: in
signal start
: in
Implement
Coverage analysis
o Current coverage status
o Coverage holes/Exclusions
o Trend analysis
o Effective tests
o Resource allocation
o Report generation
is
std_logic;
std_logic;
std_logic;
Coverage
Coverage
Coverage
db
db
db
Verify
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(Current)Analog Design and Verification
Process
We’ve got a problem here!
Product/IP
specification
o
o
o
o
o
Implement
What is the current status of the design?
Have we verified all specifications?
Who needs help?
Are we on the right track?
Report for team members/manager
More corners means
more data to Analyze
Verify
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Analog Verification Components
Analog Verification
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UCIS based CDV for Analog Design
Design/verification
specification doc
Simulation
(SPICE)
DUT (SPICE)
Testplan
EXT_SOA
Postprocessor
UCIS API
Stimulus (incl. PVT)
and cover points
Coverage
UCIS db
Merge
Questa®SIM - UCIS Framework
Coverage viewer
Coverage analysis
Coverage report
Trend analysis
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An Implementation Example
OPAMP to be used in LDO
op_en
vdd
in_n
out_p
in_p
bias_in
vss
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Specification of an OPAMP Design for a LDO
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TestPlan
#
1
1.1
1.2
1.3
1.4
2
2.1
2.2
Description
Link
AC Analysis
Gain is > 70dB
gain
3db bandwidth is > 8k Hz
3db_bw
UGB is > 10Mhz
ugb
Phase margin > 60 deg
ph_margin
Transient analysis
SlewRate > 100V/us
slewrate
rise_delay -- rise vin to rise vout delay between 1ps rise_delay
and 1ns
Type
Assertion
Assertion
Assertion
Assertion
Assertion
Assertion
Weight Goal Response Checking
1 100
1 100
1 100 spice sim
1 100 spice sim
1 100 spice sim
1 100
1 100 spice sim
1 100 spice sim
Priority Responsible
atpandey
1 atpandey
1 atpandey
1 atpandey
1 atpandey
atpandey
2.3 overshoot above logic level
2.4 undershoot below logic level
2.5 Quiescent power in power down mode <1nW
overshoot
undershoot
qp_pd
Assertion
Assertion
Assertion
1
1
1
100 spice sim
100 spice sim
100 spice sim
1 atpandey
1 atpandey
1 atpandey
2.6 Quiescent power in active mode <1uW
qp_amd
Assertion
1
100 spice sim
1 atpandey
2.7 Max power in active mode <10uW
2.8 check on all nmos devices that VDS <1.2
mxp_amd
Assertion
ovstress_n_ch Assertion
eck
1
1
100 spice sim
100 spice sim
1 atpandey
1 atpandey
2.9 check on all pmos devices that VDS <1.2
ovstress_p_ch Assertion
eck
1
100 spice sim
1 atpandey
Assertion
1
1
100
100 spice sim
1 atpandey
3.2 value of max dc current in dc analysis : upper limit ivdd_max
100u
Assertion
1
100 spice sim
1 atpandey
3.3 max dc power < 10uW
Assertion
1
3 DC Analysis
3.1 offset , crossing point at 0, should be less than 5mV offset
mxp_dc
©100
2010spice
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atpandey
TestPlan
Waveform postprocessing
Coverage
db
Simulation A (ex. Transient)
Simulation N (ex. AC ,PVT,Yield)
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Coverage Analysis
Coverage Status at certain design stage
Coveragewww.mentor.com
status at Later design stage
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Novel Aspects of this work

Compatible coverage based verification between Analog
and Digital design verification
— Coverage generation and analysis infrastructure is common
between Analog and Digital design
— Information exchange format is UCIS

Unique characteristics of analog design and verification
are addressed
— Use of existing language and tool for analog design
— Can be basis of Regression data Management/Analysis

Scalable to most analog designs

Design debug information is annotated

Extendable to cover Physical Specification/Verification
requirements
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Questions?
Coverage Driven verification
Digital Design
Analog Design
Executable Process Management and Tracking
For Mixed-Signal designs
Coverage viewer
Coverage analysis
Coverage report
Trend analysis
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References

[1] Alon Gluska: Coverage-Oriented Verification of Banias, Design Automation
Conference, 2003. Proceedings
[2] Andrew Piziali: Functional Verification Coverage Measurement and Analysis;

[3] G. Al Sammane, M.H. Zaki, Z.J. Dong and S. Tahar: Towards Assertion Based

[4] Unified Coverage Interoperability Standard:

Springer link
Verification of Analog and Mixed Signal Designs Using PSL; Proc. Languages for
Formal Specification and Verification, Forum on Specification & Design Languages
(FDL'07), Barcelona, Spain, September 2007, pp. 293-298

http://www.accellera.org/activities/committees/ucis
[5] Eldo® Reference Manual: online, www.supportnet.mentor.com
[6] Questa® SIM User’s Manual: online, www.supportnet.mentor.com

[7] UCIS standard 1.0:


http://www.accellera.org/downloads/standards/ucis/UCIS_Version_1.0_Final_June
-2012.pdf
[8] Willy M. C. Sansen, Measurement of Operational Amplifier Characteristics in
the Frequency Domain, IEEE Transactions on Instrumentation and Measurements,
Vol. 1M-34, No. I, March 1985
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Coverage Driven Verification based on UCIS
UCIS is an Accellera standard [4]
 Facilitates interoperability between various
coverage sources & tools
 Standard coverage models for commonly
used metrics
 Extendable to add user defined attributes
 Used as the basis of coverage
infrastructure in this work

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