Transcript Chapter 4 Combinational Logic - Princess Sumaya University for

Princess Sumaya Univ.
Computer Engineering Dept.
Chapter 4:
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Combinational Circuits
Output is function of input only
i.e. no feedback
n inputs
•
•
•
Combinational
Circuits
•
•
•
m outputs

When input changes, output may change (after a delay)
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Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Combinational Circuits
Analysis
● Given a circuit, find out its function
A
B
C
F1
?
F2
?
A
B
C
A
B
● Function may be expressed as:
A
C
B
C
♦ Boolean function
♦ Truth table
Design
● Given a desired function, determine its circuit
● Function may be expressed as:
♦ Boolean function
?
♦ Truth table
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4241 – Digital Logic Design
Computer Engineering Dept.
Analysis Procedure
Boolean Expression Approach
A
B
C
A
B
C
F1
ABC
A+B+C
AB'C'+A'BC'+A'B'C
A
B
(A’+B’)(A’+C’)(B’+C’)
A
C
B
C
F2
AB+AC+BC
F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
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Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Analysis Procedure
Truth Table Approach
A =0
B =0
C =0
0
A =0
B =0
C =0
0
A =0
B =0
0
A =0
C =0
0
B =0
C =0
0
0
A B C
0 0 0
F1
0
F2
0
F1
0
1
0
F2
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Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Analysis Procedure
Truth Table Approach
A =0
B =0
C =1
0
A =0
B =0
C =1
1
A =0
B =0
0
A =0
C =1
0
B =0
C =1
0
1
F1
A B C
0 0 0
0 0 1
F1
0
1
F2
0
0
1
1
0
F2
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Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Analysis Procedure
Truth Table Approach
A =0
B =1
C =0
0
A =0
B =1
C =0
1
A =0
B =1
0
A =0
C =0
0
B =1
C =0
0
1
F1
A
0
0
0
B
0
0
1
C
0
1
0
F1
0
1
1
F2
0
0
0
1
1
0
F2
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Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Analysis Procedure
Truth Table Approach
A =0
B =1
C =1
0
A =0
B =1
C =1
1
A =0
B =1
0
A =0
C =1
0
B =1
C =1
1
0
F1
0
A
0
0
0
0
B
0
0
1
1
C
0
1
0
1
F1
0
1
1
0
F2
0
0
0
1
0
1
F2
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Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Analysis Procedure
Truth Table Approach
A =1
B =0
C =0
0
A =1
B =0
C =0
1
A =1
B =0
0
A =1
C =0
0
B =0
C =0
0
1
F1
1
1
0
A
0
0
0
0
1
B
0
0
1
1
0
C
0
1
0
1
0
F1
0
1
1
0
1
F2
0
0
0
1
0
F2
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Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Analysis Procedure
Truth Table Approach
A =1
B =0
C =1
0
A =1
B =0
C =1
1
A =1
B =0
0
A =1
C =1
1
B =0
C =1
0
0
F1
0
0
1
A
0
0
0
0
1
1
B
0
0
1
1
0
0
C
0
1
0
1
0
1
F1
0
1
1
0
1
0
F2
0
0
0
1
0
1
F2
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Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Analysis Procedure
Truth Table Approach
A =1
B =1
C =0
0
A =1
B =1
C =0
1
A =1
B =1
1
A =1
C =0
0
B =1
C =0
0
0
F1
0
0
1
A
0
0
0
0
1
1
1
B
0
0
1
1
0
0
1
C
0
1
0
1
0
1
0
F1
0
1
1
0
1
0
0
F2
0
0
0
1
0
1
1
F2
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Computer Engineering Dept.
Analysis Procedure
Truth Table Approach
A =1
B =1
C =1
1
A =1
B =1
C =1
1
A =1
B =1
1
A =1
C =1
1
B =1
C =1
1
1
F1
0
0
1
F2
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
B
A
F1
0
1
1
0
1
0
0
1
C
0
1
0
1
0
1
0
1
F2
0
0
0
1
0
1
1
1
B
0
1
0
1
1
0
1
0
C
F1=AB'C'+A'BC'+A'B'C+ABC
A
0
0
1
0
0
1
1
1
C
F2=AB+AC+BC
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Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Design Procedure
Given a problem statement:
● Determine the number of inputs and outputs
● Derive the truth table
● Simplify the Boolean expression for each output
● Produce the required circuit
Example:
Design a circuit to convert a “BCD” code to “Excess 3” code
 4-bits
 0-9 values
?
 4-bits
 Value+3
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Design Procedure
BCD-to-Excess 3 Converter
A B
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
w
0
0
0
0
0
1
1
1
1
1
x
x
x
x
x
x
x
0
1
1
1
1
0
0
0
0
1
x
x
x
x
x
x
y
1
0
0
1
1
0
0
1
1
0
x
x
x
x
x
x
z
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x
A
x
1
1
x
1
C
1
x
x
C
1
x
x
B
A
1
x
1
1
1
x
1
x
x
x
x
D
D
x = B’C+B’D+BC’D’
w = A+BC+BD
C
A
1
1
x
1
1
1
x
x
x
B
C
x
x
B
A
1
1
x
1
D
y = C’D’+CD
x
x
x
1
1
x
x
B
D
z = D’
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4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Design Procedure
BCD-to-Excess 3 Converter
A B
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
w
0
0
0
0
0
1
1
1
1
1
x
x
x
x
x
x
x
0
1
1
1
1
0
0
0
0
1
x
x
x
x
x
x
y
1
0
0
1
1
0
0
1
1
0
x
x
x
x
x
x
z
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x
A
w
x
B
C
y
D
z
w = A + B(C+D)
x = B’(C+D) + B(C+D)’
y = (C+D)’ + CD
z = D’
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Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Seven-Segment Decoder
a
w
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
abcdefg
1111110
0110000
1101101
1111001
0110011
1011011
1011111
1110000
1111111
1111011
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
w
x
y
z
a
b
c
d
e
f
g
?
f
g
e
b
c
BCD code
d
y
1
w
x
1
1
1
x
x
1
x
1
1
1
x
x
x
z
a = w + y + xz + x’z’
b=...
c=...
d=...
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4241 – Digital Logic Design
Computer Engineering Dept.
Binary Adder
Half Adder
x
y
● Adds 1-bit plus 1-bit
● Produces Sum and Carry
x y
0
0
1
1
0
1
0
1
C
0
0
0
1
S
0
1
1
0
HA
S
C
x
+ y
───
C S
x
S
y
C
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4241 – Digital Logic Design
Computer Engineering Dept.
Binary Adder
Full Adder
x
y
z
● Adds 1-bit plus 1-bit plus 1-bit
● Produces Sum and Carry
x y
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
z
0
1
0
1
0
1
0
1
C
0
0
0
1
0
1
1
1
S
0
1
1
0
1
0
0
1
y
x
0
1
0
1
1
0
1
0
FA
S
C
x
+ y
+ z
───
C S
z
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
y
0
0
1
0
x
0
1
1
1
z
C = xy + xz + yz
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Computer Engineering Dept.
Binary Adder
Full Adder
x
y
x
y
z
x
y
z
x
y
z
x
y
z
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
C = xy + xz + yz
S
x
y
x
y
z
x
z
z
C
x
y
z
S
x
y
x
z
C
y
z
y
z
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Computer Engineering Dept.
Binary Adder
Full Adder
x
y
z
HA
HA
S
C
x
S
y
C
z
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Binary Adder
x3x2x1x0
y3y2y1y0
Binary Adder
Cy
C0
Carry
Propagate
Addition
c 3 c2 c1 .
+ x3 x 2 x 1 x 0
+ y3 y 2 y 1 y 0
────────
Cy S3 S2 S1 S0
S3S2S1S0
x3
x2
y3
x1
y1
y2
x0
y0
0
FA
C4
S3
FA
C3
S2
FA
C2
S1
FA
C1
S0
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Computer Engineering Dept.
Binary Adder
Carry Propagate Adder
x7 x6 x5 x4
y7 y6 y5 y4
A3 A2 A1 A0 B3 B2 B1 B0
Cy
CPA
C0
x3 x2 x1 x0
y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0
Cy
CPA
S3 S2 S1 S0
S3 S2 S1 S0
S7 S6 S5 S4
S3 S2 S1 S0
C0
0
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Computer Engineering Dept.
BCD Adder
4-bits plus 4-bits
 Operands and Result: 0 to 9
X +Y x3 x2 x1 x0
0+0 0 0 0 0
0+1 0 0 0 0
0+2 0 0 0 0
y3 y2 y1 y0 Sum
0 0 0 0 =0
0 0 0 1 =1
0 0 1 0 =2
0+9
1+0
1+1
0 0 0 0
0 0 0 1
0 0 0 1
1 0 0 1
0 0 0 0
0 0 0 1
=9
=1
=2
1+8
1+9
2+0
0 0 0 1
0 0 0 1
0 0 1 0
1 0 0 0
1 0 0 1
0 0 0 0
9+9
1 0 0 1
+ x3 x 2 x 1 x 0
+ y3 y 2 y 1 y 0
────────
Cy S3 S2 S1 S0
Cy
0
0
0
S3 S2 S1 S0
0 0 0 0
0 0 0 1
0 0 1 0
0
0
0
1 0 0 1
0 0 0 1
0 0 1 0
=9 0
=A 0
=2 0
1 0 0 1
1 0 1 0
0 0 1 0
Invalid Code
1 0 0 1 = 12 1
0 0 1 0
Wrong BCD Value
0001 1000
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BCD Adder
X +Y
x3 x2 x1 x0
y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Required BCD Output Value
9+0
9+1
9+2
9+3
9+4
9+5
9+6
9+7
9+8
9+9
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
=9
= 10
= 11
= 12
= 13
= 14
= 15
= 16
= 17
= 18
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
=9
= 16
= 17
= 18
= 19
= 20
= 21
= 22
= 23
= 24









+6
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4241 – Digital Logic Design
Computer Engineering Dept.
BCD Adder
Correct Binary Adder’s Output (+6)
● If the result is between ‘A’ and ‘F’
● If Cy = 1
S3 S2 S1 S0
0 0 0 0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Err
0
0
0
1
1
1
1
1
1
S1
S3
1
1
1
1
1
1
S2
S0
Err = S3 S2 + S3 S1
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BCD Adder
x3 x2 x1 x0
y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0
0
Err
0
0
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0
Cy
0
S3 S2 S1 S0
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Binary Subtractor
Use 2’s complement with binary adder
● x – y = x + (-y) = x + y’ + 1
x3 x2 x1 x0
y3
y2
y1
y0
A3 A2 A1 A0 B3 B2 B1
Cy
Binary Adder
S3 S2 S1 S0
B0
Ci
1
F3 F2 F1 F0
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Binary Adder/Subtractor
M: Control Signal (Mode)
● M=0  F = x + y
x3 x2 x1 x0
y3
y2
y1
y0
M
● M=1  F = x – y
A3 A2 A1 A0 B3 B2 B1
Cy
Binary Adder
S3 S2 S1 S0
B0
Ci
F3 F2 F1 F0
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Overflow
Unsigned Binary Numbers
x
x2
3
y3
x1
y2
x0
y0
y1
0
FA
Carry
C4
S3
FA
C3
S2
FA
C2
S1
FA
C1
S0
2’s Complement Numbers
x3
x2
y3
x1
y2
x0
y0
y1
0
FA
Overflow
C4
S3
FA
C3
S2
FA
C2
S1
FA
C1
S0
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Magnitude Comparator
Compare 4-bit number to 4-bit number
● 3 Outputs: < , = , >
● Expandable to more number of bits
x3  A3 B3  A3 B3
x2  A2 B2  A2 B2
x1  A1 B1  A1 B1
x0  A0 B0  A0 B0
A3A2A1A0 B3B2B1B0
Magnitude
Comparator
A<B A=B A>B
( A  B)  x3 x2 x1 x0
( A  B)  A3 B3  x3 A2 B2  x3 x2 A1 B1  x3 x2 x1 A0 B0
( A  B)  A3 B3  x3 A2 B2  x3 x2 A1 B1  x3 x2 x1 A0 B0
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Magnitude Comparator
A3
x3
B3
A2
x2
B2
(A<B)
A1
x1
B1
A0
x0
(A>B)
B0
(A=B)
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Magnitude Comparator
x7 x6 x5 x4
0
1
0
y7 y6 y5 y4
A3 A2 A1 A0 B3 B2 B1 B0
I(A>B)
Magnitude
I(A=B)
Comparator
I(A<B)
A<B A=B A>B
x3 x2 x1 x0
y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0
I(A>B)
Magnitude
I(A=B)
Comparator
I(A<B)
A<B A=B A>B
A<B A=B A>B
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Decoders
Extract “Information” from the code
 Binary Decoder
Only one
lamp will
turn on
● Example: 2-bit Binary Number
x1
0
x0 0
1
0
Binary
Decoder 0
0
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Decoders
I1
I0
I1 I0
0
0
1
1
0
1
0
1
Binary
Decoder
2-to-4 Line Decoder
Y2
y3
y2
y1
y0
Y1
Y0
Y3 Y2 Y1 Y0
0
0
0
1
0
0
1
0
Y3
0
1
0
0
1
0
0
0
I1
I0
Y3  I1 I 0
Y2  I1 I 0
Y1  I1 I 0
Y0  I1 I 0
33 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Decoders
I2
I1
I0
Binary
Decoder
3-to-8 Line Decoder
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
I2
I1
I0
Y7
 I 2 I1 I 0
Y6
 I 2 I1 I 0
Y5
 I 2 I1 I 0
Y4
 I 2 I1 I 0
Y3
 I 2 I1 I 0
Y2
 I 2 I1 I 0
Y1
 I 2 I1 I 0
Y0
 I 2 I1 I 0
34 / 65
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Decoders
Binary
Decoder
“Enable” Control
I1
I0
E
Y3
Y3
Y2
Y1
Y0
Y2
Y1
Y0
E
I1 I0
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
Y3 Y2 Y1 Y0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
I1
I0
E
35 / 65
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Decoders
Expansion
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
I0
I1
E
I0
I1
E
Binary
Decoder
I2 I1 I0
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Binary
Decoder
I2 I1 I0
Y3
Y2
Y1
Y0
Y3
Y2
Y1
Y0
36 / 65
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Decoders
Active-High / Active-Low
I1 I0 Y 3 Y 2 Y 1 Y 0
I1 I0 Y 3 Y 2 Y 1 Y 0
0
0
1
1
0
0
1
1
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
1
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
Y3
I0
Y3
Y2
Y1
Y0
I1
I0
Binary
Decoder
I1
Binary
Decoder
Y2
Y3
Y2
Y1
Y0
Y1
Y0
I1
I0
37 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Implementation Using Decoders
Each output is a minterm
 All minterms are produced
Binary
Decoder
Sum the required minterms
Example: Full Adder
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
x
y
z
I2
I1
I0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
S
C
38 / 65
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Implementation Using Decoders
x
y
z
Binary
Decoder
Binary
Decoder
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
I2
I1
I0
x
y
z
S
C
I2
I1
I0
S
C
39 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Encoders
Put “Information” into code
Only one
switch
should be
activated
at a time
 Binary Encoder
● Example: 4-to-2 Binary Encoder
x1
x2
x3
Binary
Encoder
y1
y0
x3 x2 x1
y1 y0
0
0
0
1
0
0
1
1
0
0
1
0
0
1
0
0
0
1
0
1
40 / 65
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Octal-to-Binary Encoder (8-to-3)
I7
0
0
0
0
0
0
0
1
I6
0
0
0
0
0
0
1
0
I5
0
0
0
0
0
1
0
0
I4
0
0
0
0
1
0
0
0
I3
0
0
0
1
0
0
0
0
I2
0
0
1
0
0
0
0
0
I1
0
1
0
0
0
0
0
0
Y2  I 7  I 6  I 5  I 4
Y1  I 7  I 6  I 3  I 2
Y0  I 7  I 5  I 3  I1
I0
1
0
0
0
0
0
0
0
Y2 Y1 Y0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
I7
I6
I5
I4
I3
I2
I1
I0
I7
I6
I5
I4
I3
I2
I1
I0
Binary
Encoder
Encoders
Y2
Y1
Y0
Y2
Y1
Y0
41 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Priority Encoders
I3 I2 I1 I0
0
0
0
0
1
0
0
0
1
x
I1
Y1
1 1 1 1
I3
0
0
1
x
x
1 1 1 1
1 1 1 1
I0
0
1
x
x
x
Y1 Y0 V
0 0 0
0 0 1
0 1 1
1 0 1
1 1 1
Y1  I 3  I 2
I2
Y0  I 3  I 2 I1
V  I 3  I 2  I1  I 0
I3
I2
I1
I0
I3
I2
Priority
Encoder
4-Input Priority Encoder
V
Y1
Y0
Y0
I1
Y1
I0
V
42 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Encoder / Decoder Pairs
Binary
Encoder
I7
I6
I5
I4
I3
I2
I1
I0
Y2
Y1
Y0
Binary
Decoder
I2
I1
I0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
43 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Multiplexers
S1 S0
Y
0
0
1
1
I0
I1
I2
I3
0
1
0
1
I0
I1
MUX Y
I2
I3
S1 S0
44 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Multiplexers
2-to-1 MUX
I0
I0
MUX Y
I1
S
Y
I1
S
4-to-1 MUX
I0
I1
MUX Y
I2
I3
S1 S0
I0
I1
Y
I2
I3
S1
S0
45 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Multiplexers
Quad 2-to-1 MUX
A3
Y3
x3
x2
x1
x0
A2
y3
y2
I0
MUX Y
I1
S
I0
MUX Y
I1
S
Y2
A1
Y1
A0
Y0
B3
B2
A3
A2
A1
A0
B1
y1
I0
MUX Y
I1
S
y0
I0
MUX Y
I1
S
B0
S
E
Y3
Y
MUX 2
Y1
B3
Y0
B2
B1
B0
S E
S
46 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Multiplexers
Quad 2-to-1 MUX
A3
Y3
A2
Y2
A1
Y1
A0
Y0
B3
B2
B1
B0
A3
A2
A1
A0
Y3
Y2
MUX
Y1
B3
Y0
B2
B1
B0
S E
Extra
Buffers
S
E
47 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Implementation Using Multiplexers
Example
F(x, y) = ∑(0, 1, 3)
x y
F
0
0
1
1
1
1
0
1
0
1
0
1
1
1
0
1
I0
I1
MUX Y
I2
I3
S1 S0
F
x y
48 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Implementation Using Multiplexers
Example
F(x, y, z) = ∑(1, 2, 6, 7)
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
F
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
I0
I1
I2
I3
Y
I4 MUX
I5
I6
I7
S2 S1 S0
F
x y z
49 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Implementation Using Multiplexers
Example
F(x, y, z) = ∑(1, 2, 6, 7)
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
F
0
1
1
0
0
0
1
1
F=z
F=z
F=0
z
z
0
1
I0
I1
MUX Y
I2
I3
S1 S0
F
x y
F=1
50 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Implementation Using Multiplexers
Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F
0
1
0
1
1
0
0
0
0
0
0
1
1
1
1
1
F=1
I0
I1
I2
I3
Y
MUX
I4
I5
I6
I7
S2 S1 S0
F=1
A B C
F=0
D
D
D
0
0
D
1
F=D
1
F=D
F=D
F=D
F=0
F
51 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Multiplexer Expansion
8-to-1 MUX using Dual 4-to-1 MUX
I0
I1
I2
I3
I4
I5
I6
I7
I0
I1
MUX Y
I2
I3
S1 S0
I0
I1
MUX Y
I2
I3
S1 S0
1 0 0
S2 S1 S0
I0
MUX Y
I1
S
Y
52 / 65
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
DeMultiplexers
Y3
Y2
I DeMUX Y
1
S S Y0
1
0
Y3
Y2
I
Y1
Y0
S1
S0
S1 S0
Y3 Y2 Y1 Y0
0
0
1
1
0
0
0
I
0
1
0
1
0
0
I
0
0
I
0
0
I
0
0
0
53 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Multiplexer / DeMultiplexer Pairs
MUX
I7
I6
I5
I4
I3
I2
I1
I0
DeMUX
Y
I
S2 S1 S0
x2 x1 x0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
S2 S1 S0
Synchronize
y 2 y1 y0
54 / 65
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
DeMultiplexers / Decoders
1
I1
I0
E
0
S1 S0
Y3 Y2 Y1 Y0
0
0
1
1
0
0
0
I
0
1
0
1
Y3
Y2
Y1
Y0
Binary
Decoder
Y3
Y2
I DeMUX Y
1
S S Y0
0
0
I
0
0
I
0
0
I
0
0
0
E
I1 I0
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
Y3 Y2 Y1 Y0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
55 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Three-State Gates
Tri-State Buffer
A
Y
C A
Y
0 x
1 0
1 1
Hi-Z
0
1
C
A
Y
 Tri-State Inverter
C
56 / 65
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Three-State Gates
A
C D
B
0
0
1
1
Y
C
Y
0
1
0
1
Hi-Z
B
A
?
Not Allowed
D
A
C
Y=
A
if C = 1
B
if C = 0
B
57 / 65
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Three-State Gates
I3
I2
Y
I1
S1
S0
E
I1
I0
E
Binary
Decoder
I0
Y3
Y2
Y1
Y0
58 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Homework
Mano
● Chapter 4
♦ 4-2
♦ 4-3
♦ 4-5
♦ 4-11
♦ 4-13
♦ 4-27
♦ 4-28
♦ 4-31
♦ 4-32
♦ 4-33
♦ 4-35
59 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Homework
Mano
4-2
Obtain the simplified Boolean expressions for output F
and G in terms of the input variables in the circuit:
A
F
B
C
D
G
60 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Homework
4-3
For the circuit shown in the “Quad 2-to-1 MUX”:
(a) Write the Boolean functions for the four outputs in
terms of the input variables
(b) If the circuit is listed in a truth table, how many rows
and columns would there be in the truth table?
4-5
Design a combinational circuit with three inputs, x, y, and
z, and three outputs, A, B, and C. When the binary input
is 0, 1, 2, or 3, the binary output is one greater than the
input. When the binary input is 4, 5, 6, or 7, the binary
output is one less than the input.
61 / 65
4241 – Digital Logic Design
Princess Sumaya University
Computer Engineering Dept.
Homework
4-11 Design a 4-bit combinational circuit incrementer. (A
circuit that adds one to a 4-bit binary number.) The
circuit can be designed using four half-adders.
4-13 The adder-subtractor circuit has the following values for
mode input M and data inputs A and B. In each case,
determine the values of the four SUM outputs and the
carry C.
(a)
(b)
(c)
(d)
(e)
M
A
B
0
0
1
1
1
0111
1000
1100
0101
0000
0110
1001
1000
1010
0001
62 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Homework
4-27 A combinational circuit is specified by the following three
Boolean functions:
F1(A, B, C) = ∑(2, 4, 7)
F2(A, B, C) = ∑(0, 3)
F3(A, B, C) = ∑(0, 2, 3, 4, 7)
Implement the circuit with a decoder constructed with
NAND gates and NAND or AND gates connected to the
decoder outputs. Use a block diagram for the decoder.
Minimize the number of inputs in the external gates.
63 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Homework
4-28 A combinational circuit is defined by the following three
Boolean functions:
F1 = x’ y’ z’ + x z
F2 = x y’ z’ + x’ y
F3 = x’ y’ z + x y
Design the circuit with a decoder and external gates.
4-31 Construct a 16  1 multiplexer with two 8  1 and one
2  1 multiplexers. Use block diagrams.
4-32 Implement the following Boolean function with a
multiplexer:
F(A, B, C, D) = ∑(0, 1, 3, 4, 8, 9, 15)
64 / 65
Princess Sumaya University
4241 – Digital Logic Design
Computer Engineering Dept.
Homework
4-33 Implement a full adder with two 4  1 multiplexers:
4-35 Implement the following Boolean function with a 4  1
multiplexer and external gates. Connect inputs A and B to
the selection lines. The input requirements for the four
data lines will be a function of variables C and D. These
values are obtained by expressing F as a function of C and
D for each of the four cases when AB = 00, 01, 10, and 11.
These functions may have to be implemented with
external gates.
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
65 / 65