Transcript output

Combinational Logic
Chapter 4
4.1 Introduction
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Logic circuits for digital systems may be
combinational or sequential.
A combinational circuit consists of logic gates
whose outputs at any time are determined
from only the present combination of inputs.
Digital Circuits
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4.2 Combinational Circuits
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Logic circuits for digital system
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Sequential circuits
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contain memory elements
the outputs are a function of the current inputs and the
state of the memory elements
the outputs also depend on past inputs
Digital Circuits
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A combinational circuits
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n
2 possible combinations of input values
n input
variables
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Combinational
Logic Circuit
m output
variables
Specific functions
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Adders, subtractors, comparators, decoders, encoders,
and multiplexers
MSI circuits or standard cells
Digital Circuits
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4-3 Analysis Procedure
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A combinational circuit
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make sure that it is combinational not sequential
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No feedback path
derive its Boolean functions (truth table)
design verification
a verbal explanation of its function
Digital Circuits
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A straight-forward procedure
F2 = AB+AC+BC
T1 = A+B+C
T2 = ABC
T3 = F2'T1
F1 = T3+T2
Digital Circuits
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F1 = T3+T2 = F2'T1+ABC
= (AB+AC+BC)'(A+B+C)+ABC
= (A'+B')(A'+C')(B'+C')(A+B+C)+ABC
= (A'+B'C')(AB'+AC'+BC'+B'C)+ABC
= A'BC'+A'B'C+AB'C'+ABC
A full-adder
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F1: the sum
F2: the carry
Digital Circuits
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The truth table
Digital Circuits
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4-4 Design Procedure
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The design procedure of combinational circuits
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State the problem (system spec.)
determine the inputs and outputs
the input and output variables are assigned symbols
derive the truth table
derive the simplified Boolean functions
draw the logic diagram and verify the correctness
Digital Circuits
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Functional description
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Boolean function
HDL (Hardware description language)
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Verilog HDL
VHDL
Schematic entry
Logic minimization
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number of gates
number of inputs to a gate
propagation delay
number of interconnection
limitations of the driving capabilities
Digital Circuits
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Code conversion example
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BCD to excess-3 code
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The truth table
Digital Circuits
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The maps
Digital Circuits
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The simplified functions
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z = D'
y = CD +C'D'
x = B'C + B'D+BC'D'
w = A+BC+BD
Another implementation
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z = D'
y = CD +C'D' = CD + (C+D)'
x = B'C + B'D+BC'D‘ = B'(C+D) +B(C+D)'
w = A+BC+BD
Digital Circuits
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The logic diagram
Digital Circuits
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4-5 Binary Adder-Subtractor
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Half adder
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0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = 10
two input variables: x, y
two output variables: C (carry), S (sum)
truth table
Digital Circuits
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S = x'y+xy'
C = xy
the flexibility for implementation
S=xy
S = (x+y)(x'+y')
S' = xy+x'y'
S = (C+x'y')'
C = xy = (x'+y')'
Digital Circuits
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Digital Circuits
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Full-Adder
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The arithmetic sum of three input bits
three input bits
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x, y: two significant bits
z: the carry bit from the previous lower significant bit
Two output bits: C, S
Digital Circuits
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Digital Circuits
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S = x'y'z+x'yz'+ xy'z'+xyz
C = xy + xz + yz
S = z (xy)
= z'(xy'+x'y)+z(xy'+x'y)'
= z'xy'+z'x'y+z((x'+y)(x+y'))
= xy'z'+x'yz'+xyz+x'y'z
C = z(xy'+x'y)+xy
= xy'z+x'yz+ xy
Digital Circuits
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Binary adder
Digital Circuits
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Carry propagation
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when the correct outputs are available
the critical path counts (the worst case)
(A1,B1,C1) > C2 > C3 > C4 > (C5,S4)
> 8 gate levels
Digital Circuits
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Reduce the carry propagation delay
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employ faster gates
look-ahead carry (more complex mechanism, yet
faster)
carry propagate: Pi = AiBi
carry generate: Gi = AiBi
sum: Si = PiCi
carry: Ci+1 = Gi+PiCi
C1 = G0+P0C0
C2 = G1+P1C1 = G1+P1(G0+P0C0)
= G1+P1G0+P1P0C0
C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0
Digital Circuits
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Logic diagram
Digital Circuits
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4-bit carry-look ahead adder
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propagation delay
Digital Circuits
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Binary subtractor
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A-B = A+(2’s complement of B)
4-bit Adder-subtractor
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M=0, A+B; M=1, A+B’+1
Digital Circuits
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Overflow
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The storage is limited
Add two positive numbers and obtain a negative
number
Add two negative numbers and obtain a positive
number
V = 0, no overflow; V = 1, overflow
Example:
Digital Circuits
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4-6 Decimal Adder
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Add two BCD's
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9 inputs: two BCD's and one carry-in
5 outputs: one BCD and one carry-out
Design approaches
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A truth table with 2^9 entries
use binary full Adders
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the sum <= 9 + 9 + 1 = 19
binary to BCD
Digital Circuits
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BCD Adder: The truth table
Digital Circuits
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Modifications are needed if the sum > 9
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C=1
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K=1
Z8Z4 = 1
Z8Z2 = 1
modification: (10)d or +6
C = K +Z8Z4 + Z8Z2
Digital Circuits
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Block diagram
Digital Circuits
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Binary Multiplier
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Partial products
– AND operations
Fig. 4.15
Two-bit by two-bit binary multiplier.
Digital Circuits
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4-bit by 3-bit binary multiplier
Fig. 4.16
Four-bit by three-bit binary
multiplier.
Digital Circuits
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4-8 Magnitude Comparator
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The comparison of two numbers
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outputs: A>B, A=B, A<B
Design Approaches
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the truth table
2n
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2 entries - too cumbersome for large n
use inherent regularity of the problem
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reduce design efforts
reduce human errors
Digital Circuits
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Algorithm -> logic
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A = A3A2A1A0 ; B = B3B2B1B0
A=B if A3=B3, A2=B2, A1=B1and A1=B1
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equality: xi= AiBi+Ai'Bi'
(A=B) = x3x2x1x0
(A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'
(A>B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0
Implementation
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xi = (AiBi'+Ai'Bi)'
Digital Circuits
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Fig. 4.17
Four-bit magnitude comparator.
Digital Circuits
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4-9 Decoder
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A n-to-m decoder
n
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a binary code of n bits = 2 distinct information
n
n input variables; up to 2 output lines
only one output can be active (high) at any time
Digital Circuits
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An implementation
Fig. 4.18
Three-to-eight-line decoder.
Digital Circuits
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Combinational logic implementation
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each output = a minterm
use a decoder and an external OR gate to
implement any Boolean function of n input
variables
Digital Circuits
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Demultiplexers
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a decoder with an enable input
receive information on a single line and transmits
n
it on one of 2 possible output lines
Fig. 4.19
Two-to-four-line decoder with enable input
Digital Circuits
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Decoder/demultiplexers
第三版內容，參考用!
Digital Circuits
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Expansion
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two 3-to-8 decoder: a 4-to-16 deocder
Fig. 4.20
4  16 decoder
constructed with two
3  8 decoders
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a 5-to-32 decoder?
Digital Circuits
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Combination Logic Implementation
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each output = a minterm
use a decoder and an external OR gate to
implement any Boolean function of n input
variables
A full-adder
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S(x,y,x)=S(1,2,4,7)
C(x,y,z)= S(3,5,6,7)
Fig. 4.21
Implementation of a full adder with a decoder
Digital Circuits
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two possible approaches using decoder
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OR(minterms of F): k inputs
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NOR(minterms of F'): 2  k inputs
n
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In general, it is not a practical implementation
Digital Circuits
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4-10 Encoders
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The inverse function of
a decoder
z  D1  D3  D5  D7
y  D2  D3  D6  D7
x  D4  D5  D6  D7
The encoder can be implemented
with three OR gates.
Digital Circuits
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An implementation
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limitations
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illegal input: e.g. D3=D6=1
the output = 111 (¹3 and ¹6)
第三版內容，參考用!
Digital Circuits
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Priority Encoder
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resolve the ambiguity of illegal inputs
only one of the input is encoded
D3 has the highest priority
D0 has the lowest priority
X: don't-care conditions
V: valid output indicator
Digital Circuits
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■ The maps for simplifying outputs x and y
Fig. 4.22
Maps for a priority encoder
Digital Circuits
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■ Implementation of priority
Fig. 4.23
Four-input priority encoder
x  D2  D3
y  D3  D1D2
V  D0  D1  D2  D3
Digital Circuits
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4-11 Multiplexers
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select binary information from one of many input
lines and direct it to a single output line
n
2 input lines, n selection lines and one output line
e.g.: 2-to-1-line multiplexer
Fig. 4.24
Two-to-one-line multiplexer
Digital Circuits
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4-to-1-line multiplexer
Fig. 4.25
Four-to-one-line multiplexer
Digital Circuits
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Note
n
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n-to- 2 decoder
n
add the 2 input lines to each AND gate
OR(all AND gates)
an enable input (an option)
Digital Circuits
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Fig. 4.26
Quadruple two-to-one-line multiplexer
Digital Circuits
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Boolean function implementation
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MUX: a decoder + an OR gate
n
2 -to-1 MUX can implement any Boolean function
of n input variable
a better solution: implement any Boolean function
of n+1 input variable
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n of these variables: the selection lines
the remaining variable: the inputs
Digital Circuits
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an example: F(A,B,C) = S(1,2,6,7)
Fig. 4.27
Implementing a Boolean function with a multiplexer
Digital Circuits
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Procedure:
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assign an ordering sequence of the input variable
the rightmost variable (D) will be used for the input
lines
assign the remaining n-1 variables to the selection
lines w.r.t. their corresponding sequence
construct the truth table
consider a pair of consecutive minterms starting
from m0
determine the input lines
Digital Circuits
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Example: F(A, B, C, D) = S(1, 3, 4, 11, 12, 13, 14, 15)
Fig. 4.28
Implementing a four-input function with a multiplexer
Digital Circuits
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Three-state gates
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A multiplexer can be constructed with three-state
gates
Output state: 0, 1, and high-impedance (open ckts)
Fig. 4.29
Graphic symbol for a three-state buffer
Digital Circuits
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Example: Four-to-one-line multiplexer
Fig. 4.30
Multiplexer with three-state gates
Digital Circuits
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4-12 HDL Models of Combinational Circuits
▓ Modeling Styles:
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Gate-level Modeling
▓ The four-valued logic truth tables for the and, or, xor, and
not primitives
Digital Circuits
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Gate-level Modeling
Example:
output [0: 3] D;
wire
[7: 0] SUM;
1. The first statement declares an output vector D with four bits, 0
through 3.
2. The second declares a wire vector SUM with eight bits numbered 7
through 0.
Digital Circuits
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HDL Example 4-1
■ Two-to-one-line decoder
Digital Circuits
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HDL Example 4-2
■ Four-bit adder: bottom-up hierarchical description
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HDL Example 4-2 (continued)
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Three-State Gates
■ Statement:
gate name (output, input, control);
Fig. 4.31
Three-state gates
Digital Circuits
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Three-State Gates
■ Examples of gate instantiation
Digital Circuits
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Fig. 4.32
Two-to-one-line
multiplexer with
three-state buffers
Digital Circuits
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Dataflow Modeling
■ Verilog HDL operators
Example:
assign Y = (A & S) | (B & ~S)
Digital Circuits
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HDL Example 4.3
 Dataflow description of a 2-to-4-line decoder
Digital Circuits
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HDL Example 4-4
 Dataflow description of 4-bit adder
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HDL Example 4-5
 Dataflow description of 4-bit magnitude comparator
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HDL Example 4-6
 Dataflow description of a 2-to-1-line multiplexer
 Conditional operator (?:)
Condition ? True-expression : false-expression
Example: continuous assignment
assign OUT = select ? A : B
Digital Circuits
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Behavioral Modeling
 if statement:
if (select) OUT = A;
HDL Example 4-7
 Behavioral description of a 2-to-1-line multiplexer
Digital Circuits
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HDL Example 4-8
 Behavioral description of a 4-to-1-line multiplexer
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Writing a Simple Test Bench
 initial block
Three-bit truth table
Digital Circuits
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Writing a Simple Test Bench
 Interaction between stimulus and design modules
Digital Circuits
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Writing a Simple Test Bench
 Stimulus module
 System tasks for display
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 Syntax for $dispaly, $write, and $monitor:
Example:
Example:
Digital Circuits
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HDL Example 4-9
 Stimulus module
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HDL Example 4-9 (Continued)
Digital Circuits
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HDL Example 4-10
 Gate-level description of a full adder
Digital Circuits
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HDL Example 4-10 (Continued)
Digital Circuits
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