Transcript Lab5

Programmable Logic
System Design
Lab05
- Component & Generate
SOCLAB
Yu-Xuan Peng
2013.11
Lab Description
實驗要求:
1. 撰寫一個 1 bit 的 2-to-1 MUX VHDL code
2. 設計一個 5-to-1 MUX，並撰寫 Testbench 進行模擬
3. 將設計的 5-to-1 MUX 燒進 FPGA 板子進行驗證
Example: 4-TO-1 MUX
此多工器有6個輸入及1個輸出，
資料為 1 bit ,其結構和真值表如
下所示。
LIBRARY ieee;
USEieee.std_logic_1164.all;
ENTITY mux4to1 IS PORT
( w0,w1,w2,w3 :IN STD_LOGIC;
s :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
f :OUT STD_LOGIC);
END mux4to1;
ARCHITECTURE Behavior OF mux4to1 IS
BEGIN
WITH s SELECT
f <= w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS;
END Behavior;
Example: 16-TO-1 MUX
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux16to1 IS
PORT ( w :IN STD_LOGIC_VECTOR(0 TO 15);
s :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
f :OUT STD_LOGIC);
END mux16to1;
ARCHITECTURE Structure OF mux16to1 IS
COMPONENT mux4to1
PORT ( w0,w1,w2,w3 :IN STD_LOGIC;
s :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
f :OUT STD_LOGIC);
END COMPONENT;
SIGNAL m:STD_LOGIC_VECTOR(0 TO 3);
BEGIN
MUX1: mux4to1 PORT MAP(w(0),w(1),w(2),w(3),s(1 DOWNTO 0),m(0));
MUX2: mux4to1 PORT MAP(w(4),w(5),w(6),w(7),s(1 DOWNTO 0),m(1));
MUX3: mux4to1 PORT MAP(w(8),w(9),w(10),w(11),s(1 DOWNTO 0),m(2));
MUX4: mux4to1 PORT MAP(w(12),w(13),w(14),w(15),s(1 DOWNTO 0),m(3));
MUX5: mux4to1 PORT MAP(m(0),m(1),m(2),m(3),s(3 DOWNTO 2),f);
END Structure;
(Use “component” syntax)
Example: 16-TO-1 MUX
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux16to1 IS
PORT ( w :IN STD_LOGIC_VECTOR(0 TO 15);
s :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
f :OUT STD_LOGIC);
END mux16to1;
ARCHITECTURE Structure OF mux16to1 IS
COMPONENT mux4to1
PORT ( w0,w1,w2,w3 :IN STD_LOGIC;
s :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
f :OUT STD_LOGIC);
END COMPONENT;
SIGNAL m:STD_LOGIC_VECTOR(0 TO 3);
BEGIN
G1: FOR i IN 0 TO 3 GENERATE
MUXES: mux4to1 PORT MAP(
w(4*i),w(4*i+1),w(4*i+2),w(4*i+3),s(1 DOWNTO 0),m(i));
END GENERATE;
MUX5: mux4to1 PORT MAP(m(0),m(1),m(2),m(3),s(3 DOWNTO 2),f);
END Structure;
(Use “generate” syntax )
Assignment
1.先將 5-to-1 MUX 設計出來，並將 block diagram 畫下來
2.完成一個 1 bit 的 2-to-1 MUX VHDL code
3.利用”component” 和”generate”的語法，完成一個 5-to-1 MUX
4.請自行撰寫Testbench進行模擬，並demo模擬結果
5.以指撥開關給定五個輸入訊號，再以三個開關控制”選擇”的信號，
將輸出信號(1 bit)輸出於一個led燈顯示
6.將程式燒錄到版子之後，撥動開關輸入訊號
7.完成後進行demo
結報問題
 請把設計出的 5-to-1 MUX 的詳細接線圖畫在
結報中，並舉一個例子說明功能。