Transcript Sales Conference Creative Template

Design AXI Master
Page 1
XILINX CONFIDENTIAL
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Agenda
Understanding Zynq AXI Master
IP axi_user_npi
Page 2
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2012 Xilinx
XILINX
CONFIDENTIAL
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What is AXI?
AXI is Part of AMBA: Advanced
Microcontroller
Variations of AXI
Page 3
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Variations of AXI
AXI4
– Memory mapped
AXI4-Lite:
– Register mapped
AXI4-Stream:
– Streaming
Page 4
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2012 Xilinx
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Why Xilinx Choose AXI?
BRAM
LMB
External
Memory
Xilinx Cache Link
MPMC
Microblaze
VFBC
Video
TEMAC
Hardware
Accelerator
Local Link
FSL
NPI
Custom IP
PLBv46
GPIO
Page 5
Timer
SRAM
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UART
PLB to IPIF
Bridge
IPIF
Custom IP
Why Xilinx Choose AXI?
BRAM
LMB
External
Memory
AXI
MPMC
Microblaze
AXI
Video
AXI
TEMAC
Hardware
Accelerator
AXI
AXI
Custom IP
AXI
GPIO
Page 6
Timer
SRAM
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UART
AXI to IPIF
Bridge
IPIF
Custom IP
AXI Protocol, Channel
Channel
– Read address
– Write address
– Read data
– Write data
– Write response
Page 7
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AXI Protocol, AXI4
Single address multiple data
– Burst up to 256 data beats
AXI4 READ
Data width parameterizable
– 32, 64, 128, 256
AXI4 Write
Page 8
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AXI Protocol, AXI4_LITE
Single address Single data
– No Burst
AXI4-Lite Read
Data width
– 32
AXI4-Lite Write
Page 9
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AXI Protocol, AXI4_STREAM
No address channel
Not read and write, always just
master to slave
Unlimited burst length
Page 10
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ZYNQ
High Performance Port
General Performance Port
Master
AXI Master
AXI Slave
Page 11
Slave
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Master
How to Design AXI Master
CIP
Select AXI type
Select Master
Page 12
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How to Design AXI Master, example
MPD
– Default parameter
PAO
– Order for synthesis
TEST_IP.VHD
– Top level
USER_LOGIC.VHD
– User logic
Page 13
XILINX CONFIDENTIAL
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How to Design AXI Master
User_logic.vhd
– Control
Burst Transaction
Page 14
XILINX CONFIDENTIAL
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Why Design AXI Master
To access DDRx Memory
Why don’t you use BRAM?
Because BRAM is EASY
Zynq Bram 220KB ~ 2180KB
But BRAM is TOO SMALL
DDRx is LARGE
DDRx max 1GB
But DDRx is not EASY
Page 15
XILINX CONFIDENTIAL
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FIFO Instead of IPIC
Remove Complexity
DDRx
Page 16
IPIC &
State
Machine
FIFO
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User
Logic
Master IP with FIFO, axi_user_npi
IP catalog
Bus
Port
Page 17
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Master IP with FIFO, axi_user_npi
User logic interface
– Simple
– It is FIFO
Page 18
component system is
port (
...
wr_fifo_wr_en : in std_logic;
wr_fifo_clk : in std_logic;
npi_wr_ready : out std_logic;
rd_fifo_rd_en : in std_logic;
npi_rd_ready : out std_logic;
wr_fifo_data : in std_logic_vector(31 downto 0);
rd_fifo_clk : in std_logic;
rd_fifo_full : out std_logic;
rd_fifo_data : out std_logic_vector(31 downto 0);
rd_fifo_empty : out std_logic;
wr_fifo_full : out std_logic;
wr_fifo_empty : out std_logic
);
end component;
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2012 Xilinx
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Master IP with FIFO, axi_user_npi
How to Run?
– Device Driver
Read
– Start add
– Read Burst Cnt
– Repeat Cnt
Write
– Start add
void npi_stop()
{
}
void npi_start()
{
}
void axi_npi_rd(int reg, int src, int cnt_burst, int cnt_repeat)
{
}
void axi_npi_wr(int reg, int src, int cnt_burst, int cnt_repeat)
{
}
void axi_npi_reset0()
{
}
int npi_status(int reg)
{
}
– Read Burst Cnt
– Repeat Cnt
Page 19
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Simulation Result
Burst Write
Burst Read
Page 20
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Q&A
Page 21
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2012 Xilinx
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CONFIDENTIAL
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