Transcript 期中考範圍

VLSI TESTING
積體電路測試
期中考範圍
賴秉樑
PING-LIANG LAI
1
VLSI TESTING 2011
Chapter 2-1

共考4題，每題25分
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VLSI TESTING 2011
Chapter 2-2
第一題

給定一組合電路，求出Fault Collapsing後的Fault list。
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VLSI TESTING 2011
Chapter 2-3
Fault Equivalence Rule





AND gate: all s-a-0 faults are equivalent
OR gate: all s-a-1 faults are equivalent
NAND gate: all the input s-a-0 faults and the output s-a-1 faults are equivalent
NOR gate: all input s-a-1 faults and the output s-a-0 faults are equivalent
Inverter: input s-a-1and output s-a-0 are equivalent input s-a-0 and output s-a-1
are equivalent
SA0
SA0
SA0
SA0
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SA1
SA1
SA0
SA1
SA1
SA0
SA1
SA1
SA1
SA1
SA1
SA1
SA0
SA1
SA1
SA0
SA0
SA0
SA1
SA0
SA0
SA1
SA0
SA0
n+2 instead of 2n+2 faults need to be
considered for an n-input gate.
VLSI TESTING 2011
Chapter 2-4
Fault Collapsing Summary
Given F1 and F2 with T1
and T2
 Equivalence

– F1 is equivalent to F2 if T1
= T2
– Any test detecting F1,
detects F2 and vice versa

Dominance
– F1 dominates F2 if T2  T1
– A test detecting F2 detects
also F1
– The relation is not
symmetric
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Example: NAND2
A
C
B
Inputs
Fault-free
Faulty Response
AB
C (Response)
A/0
B/0
C/0
A/1
B/1
C/1
00
1
1
1
0
1
1
1
01
1
1
1
0
0
1
1
10
1
1
1
0
1
0
1
11
0
1
1
0
0
0
1
Fault equivalence: {A/0, B/0, C/1}
Fault dominance: A/1 → C/0, B/1 → C/0
Fault collapsing: {A/0, A/1, B/1}
VLSI TESTING 2011
Chapter 2-5
An Example of Fault Collapsing

A step of collapsing
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A
B
H
{A/0, B/0, H/0}
{C/1, D/1, F/1}
G
F
C
V
{G/0, E/0, V/0}
D
{H/1, V/1, Z/1}
E
{F/0, G/1}
{F/1, G/0}
A/1 → H/1, thus A/1 can represent H/1 and all its equivalent faults in class 4
C/0 → F/0, thus C/0 can represent F/0 and all its equivalent faults in class 5
G/1 → V/1, thus G/1 can represent V/1 and all its equivalent faults in class 4
H/0 → Z/0, thus H/0 belongs to equivalence class 1
B/1 → H/1
D/0 → F/0
E/1 → V/1
V/0 → Z/0
{A/0, C/1, G/0, A/1, C/0, G/1, B/1, D/0, E/1} → Final set of fault under test
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VLSI TESTING 2011
Z
Chapter 2-6
第二題

找出Transistor Stuck-open或Stuck-short的測試向量。
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VLSI TESTING 2011
Chapter 2-7
Transistor Faults (1/4)

MOS transistor is considered as an ideal switch and two types of faults
are modeled:
– Stuck-open: a single transistor is permanently stuck in the open state
– Stuck-short: a single transistor is permanently shorted irrespective of it's gate voltage

Detection of a stuck-open fault requires a two vector sequence
Vector 2: test for A SA1
0
0
1
0
A
PMOS stuck-open fault
Faulty circuit states
B
C
Vector 1: test for A SA0
(initialization vector)
0
1 (Z)
Good circuit states
Transistor stuck-open fault
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VLSI TESTING 2011
Chapter 2-8
Transistor Faults (2/4)

Detection of a stuck-short fault requires the measurement of
quiescent current (IDDQ)
Vector 2: test for A SA0
1
0
A
PMOS stuck-short fault
Faulty circuit output
B
C
1 (X)
Good circuit output
IDDQ path in faulty circuit
Transistor stuck-short fault
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VLSI TESTING 2011
Chapter 2-9
第三題

給定一組合電路，TM。
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VLSI TESTING 2011
Chapter 2-10
An Example of Combinational Circuit (1/3)
F
G1
Y
G4
A
H
G2
B
C
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G3
G5
Z
G
VLSI TESTING 2011
Chapter 2-11
An Example of Combinational Circuit (2/3)
First, calculate the TM for the nodes on the
second level, F, H, and G
1.CC1(F)=CC1(A)+CC1(B)+CC1(C)+1=4
2.CC0(F)=min{CC0(A), CC0(B), CC0(C)}+1=2
3.CC1(H)=min{CC0(A), CC0(B)}+1=2
4.CC0(H)=CC1(A)+CC1(B)+1=3
5.CC1(G)=CC0(C)+1=2
6.CC0(G)=CC1(C)+1=2
F
G1
Y
G4
A
H
G2
B
C
G3
G5
Z
G
These TM values are then used in calculating
the primary output controllability
7.CC1(Y)=min{CC1(F), CC1(H)}+1=3
8.CC0(Y)=CC0(F)+CC0(H)+1=6
9.CC1(Z)=min{CC0(H), CC0(G)}+1=3
10.CC0(Z)=CC1(H)+CC1(G)+1=5
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VLSI TESTING 2011
Chapter 2-12
An Example of Combinational Circuit (3/3)
The observability of a node indicates the effort
needed to observe the logic value on the node at
a primary output
For second level,
11.COY(F)=CO(Y)+CCO(H)+1=5
12.COZ(G)=CO(Z)+CC1(H)+1=4
13.COY(H)=CO(Y)+CC0(F)+1=4
14.COZ(H)=CO(Z)+CC1(G)+1=5
For primary inputs,
15. COZ(C)=COZ(G)+1=[CO(Z)+CC1(H)+1]+1 =5
(line C)
16. COY(C)=COY(F)+CC1(A)+CC1(B)+1
=[CO(Y)+CC0(H)+1]+CC1(A)+CC1(B)+1=8
(line C)
17.COYH(A)=COY(H)+CC1(B)+1=6
18.COZ(A)=COZ(H)+CC1(G)+1=8
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CC1(F)=4
CC0(F)=2
CC1(H)=2
CC0(H)=3
CC1(G)=2
CC0(G)=2
CC1(Y)=3
CC0(Y)=6
CC1(Z)=3
CC0(Z)=5
F
G1
Y
G4
A
H
G2
B
C
VLSI TESTING 2011
G3
G5
Z
G
Chapter 2-13
第四題

給定一循序電路，劃出Scan DFT的設計電路。
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VLSI TESTING 2011
Chapter 2-14
Example: Scan for Binary Counters

3-bits Counter using DFF - State table
Present State
Next State
F/F Inputs
A
B
C
+A
+B
+C
DA
DB
DC
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
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VLSI TESTING 2011
As function of F(A,B,C)
DA=A⊕BC
DB=B⊕C
DC=C’
Chapter 2-15
Scan DFT for Binary Counters (1/2)

3-bits Binary Counters
Next State and Output Combinational Logic
DA=A⊕BC
DB=B⊕C
DC=C’
CUT
C
B
1
A
DC
DB
DA
CLK
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VLSI TESTING 2011
Chapter 2-16
Scan DFT for Binary Counters (2/2)
C
B
IN/SI
0
1
0
1
0
1
0
1
A/SO
CLK
SE
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VLSI TESTING 2011
Chapter 2-17
S: Shift operation
C: Capture operation
H: Hold cycle
V1:PI
SE
S
V2:PI
H
C
H
S
H
C
CLK
QC
0
1
0
0
H
H
0
1
1
1
1
QB
×
0
1
1
H
H
H
0
1
1
1
QA
×
×
0
0
L
L
H
H
0
0
1
V1:SI (PPI)
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SO (PPO) observationV2:SI (PPI)
C (PO) observation
VLSI TESTING 2011
Chapter 2-18