Transcript ppt
The 10-ps TDC implemented in
an FPGA
Jinhong Wang, Shubin Liu, and Qi An
FELab@USTC
Outline
Implementation of FPGA TDC @ USTC
Timing Performance of FPGA TDC
TDC Modules @ USTC
The Principle of the FPGA TDC
Coarse Counter (Coarse Time)+Time Interpolation within
one clock period (Fine Time)
CLK
HitIn
Coarse Time
CLK
Step[0]
D
SET
CLR
D
SET
Delay
D
SET
CLR
Q
Q
Step[1]
Q
Q
Step[2]
Q
CNT
N
N+1
Fine Time
CLR
Control
Q
Q
Temperature
Enable
Out Data
Empty
Channel ID
Delay
CLK
SET
RdClk
Q
Step[n-1]
D
Read
FIFO
CLR
CLK
Selector
Encoder Unit
Delay
Delay
Delay
Hit
Double Coarse
Latch Time Counters
Full
Implementation of the Time Interpolation
Time Interpolation with the delay of Carry lines
SLICEM SLICEL
COUT
COUT
Interconnect to Neighbors
SLICE(3)
Xm+1Yn+1
CLB
SLICE(1)
Xm+1Yn
Switch
Matrix
SLICE(2)
XmYn+1
SLICE(0)
XmYn
CIN
SLICE
X65Y100
SLICE
X65Y101
SLICE
X65Y102
CIN
a) Carry-in in a Slice
Sum[n-1]
Co[n-1]
Sum[1]
Adder
Adder
Co[n-2]
1
0
Co[1]
1
0
Co[0]
Sum[0]
Adder
1
c) Carry chain of a multibit adder
Ci=0
Hit
b) Rout in a SLICE
SLICE
X65Y103
FPGA TDC @FELab, USTC
~100 ps Bin Size, 50 ps RMS ; In the year 2005
TNS Vol.53, Issue 1 Part 2
Time interpolation with the dedicated Carry lines
~50 ps Bin Size, < 20 ps RMS ; In the year 2009
TNS Vol.57, Issue 2 Part 1
With Several Compensation Strategies: self-test, Temperature
compensation
Up to the present
~ 10 ps Bin Size (Effective) , <10 ps RMS
a Modified Wave Union TDC
The 10-ps FPGA TDC
Wave Union Launcher
MUX
OSC_Inv
Hit
1
Delay
Delay
Delay
1
2
3
INV
Delay
Delay
n-1
n
Hit_In
0
k
k+1
CLK
D
SET
CLR
Q
Q
Q
Q
Q
Step[n-1]
SET
CLR
SET
Step[k+1]
D
D
Q
Q
Q
Q
Step[k]
CLR
SET
CLR
SET
Step[3]
D
D
Q
Q
Step[2]
CLR
SET
N
Q
Q
Selector
CLR
SET
Q
Step[1]
Delay
D
D
CLR
SEL
Step[n]
Encoder
INV+Delay+MUX
Signal Processing of the Raw TDC Time
TCLK
CLK
t1
t TOSC TCLK
t3
Hit
t2
Osc.
TOSC
TOSC
tN
t01 t1
t t t
02 2
t03 t3 2t
...
t t (k 1)t
0k k
...
t0 N t N ( N 1)t
N times Oscillation
200
A
B
C
1 N
t 0 t 0i
N i 1
TDC Bin
150
100
50
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
N
Timing Performance
80
70
Uneven of the tap delay +
Uncertainty of the Osc. Period
① σosc << σcell
② σosc ≈ σcell
③ σosc >> σcell
σ =0 ps
σ =10 ps
σ =30 ps
RMS (ps)
60
3
50
40
Simulation
30
2
20
1
10
0
1
4
8
N
12
16
20
Actual implementation falls in to Case 2
RMS vs. N
18
test
1200
16
RMS: 8 ps
1000
800
12
Count
RMS (ps)
14
10
400
8
200
6
4
4
600
8
12
16
20
N
24
28
32
0
80
100
120
140
160
Time Interval (ps)
180
200
Timing Performance
Bin Size
50
Effectie Bin Size (ps)
BIN
scales as 1/N
Similar to dither
40
30
Bin VS. N
20
10
0
1
2
3
4
5
6
7
8
N
10000
N=1 N=2 N=3 N=4 N=5 N=6
N=7 N=8N=9
N=10 N=11
N=14
Fine Time (ps)
8000
N=13
N=12
6000
4000
2000
0
0
500
1000
1500
2000
Effective Fine Bin
2500
3000
9
10
11
12
13
14
FPGA TDC Module
~20 ps RMS, 50 ps Bin
NIM, USB, other platforms
Xilinx, Altera
< 10 ps RMS, 12 ps Bin (planed)
PXI, VME, USB
Xilinx Virtex 4, Virtex 5…
The 25-ps FPGA TDC Module
Altera + XILINX
<25 ps RMS, 50 ps Bin
The 10-ps FPGA TDC Module
16 + Chnl.
<10 ps RMS , ~10 ps Bin
Virtex 4 / Virtex 5, …
Platform: VME, PXI, USB 2.0
Others: Trigger Matching
Thank you ~
TDC
10-ps
TDC
20-ps
TDC
Resource Used
Available
Utilization
Slice
Register
2081
50560
4.1%
4-input
LUT
3280
50560
6.5%
Slice
Register
684
50560
1.4%
4-input
LUT
606
50560
1.2%