Transcript ppt
TIMx - Timer
MS_uC / fue1 / V01
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Programming Microcontroller
TIMx - Timer
Autumn term 2012
TIMx - Timer
MS_uC / fue1 / V01
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Typical Timer Features
Four 16 bit Timers, support:
Two Input Captures
Two Output Compares
PWM Out
PWM Input
One Pulse Mode
Two Clocks: External clocks,
Internal Events
Prescaler
DMA support
Peripheral Bus
CK_INT
TIMx_ETR
ITR0
Trigger
controller
Output
Comp. Reg 2
Output
Comp. Reg 1
Output
Comp. 2
Output
Comp. 1
Latch 2
Latch 2
Input
Cap 2
Input
Cap 1
16 Bit
Prescaler
ITR3
16-Bit
Counter
Register
Overflow
Control
Registers
Edge
Detect
Circuit 2
Edge
Detect
Circuit 1
IC1
IC2
OC1
OC2
Interrupt - Overflow, OCMP, ICAP
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STM32F107xx Timer Modules
TIM - Timer
MS_uC / fue1 / V01
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RM0008 Reference manual
Advanced-control timers: TIM1 & TIM8
16-bit up, down, up/down auto-reloat counter
4 Indepent channels
Input capture, Output compare, PWM & OPM
Complementary outputs with programmable dead time
General-purpose timers (TIM2 to TIM5)
16-bit up, down, up/down auto-reloat counter
4 Indepent channels
General-purpose timers (TIM9 to TIM14)
16-bit up, down, up/down auto-reloat counter
2 Indepent channels
Basic Timers (TIM6 & TIM7)
16-bit up, down, up/down auto-reloat counter
TIM - Timer
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General-purpose timers main
features (1/2)
16-bit up, down, up/down auto reload counter
Provide counter values for output compare and input capture
16-bit programmable pre scaler used to divide the counter clock
frequency by any factor between 1 and 65’535
Up to 4 independent channels for:
Input capture
Output compare
PWM generation
One pulse mode output
Synchronization circuit to control the timer with external signals and to
interconnect several timers
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TIM - Timer
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General-purpose timers main
features (2/2)
Interrupt/DMA generation on the following events
Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
Trigger event (counter start, stop, initialization or count by internal/external
trigger)
Input capture
Output compare
Supports incremental (quadrature) encode and hall-sensor circuitry for
positioning purposes
Trigger input for external clock or cycle-by cycle current management
TIM - Timer
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TIMx modes of functionality
Input Capture Mode
Two input pins, user programmable edge polarity
Capture counter values when input edge is detected
Generate interrupt when enabled
Can measure input pulse width
Output Compare Mode
Two output compare pins, one for each compare register
Compare Register is compared with counter value
Generate output signal/waveform on pin when a match occurred
User programmable output signal level
Other Timer Modes
Based on the Input Capture and Output Compare logic
One Pulse Mode
PWM Output Mode
PWM Input Mode
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TIM - Timer
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TIMx PWM output mode
Automatic generation of a Pulse Width Modulated signal
Frequency determined by TIMx_ARR register
Duty cycle corresponds to TIMx_CCRx register
Counter
34E2
0000
0001
0002
2ED0
2ED1
CC1P = 0
CC1P = 0
OC1
Compare 2
…
Compare 1
34E2
0000
OLVL2
Compare 2
TIMx_CCR1 = 0x2ED0
TIMx_ARR = 0x34E2
CC1P = 0
Configuration for the PWM output mode
OCxM bits in the TIMx_CCMRx register selects the PWM output mode for OCx
OCxPE bit in the TIM_CCMRx register enables the corresponding preload register
ARPE bit in the TIMCR1 register enables auto-reload preload register
CCxP bit in the TIM_CCER register defines the polarity of the OCx output
CCxE bit in the TIM_CCER register enable the OCx output
The duty cycle is stored in TIMx_CCR1 register
The full period is stored in TIMx_ARR register
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TIMx PWM input mode
TIM - Timer
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External pulse and period measurement of an external wave
Programmable first edge detection
Interrupt Generation
Counter
34E2
0000
0001
0002
2ED0
2ED1
TI1
IC1 capture
Pulse Length = TIMx_CCR1
IC2 capture
Period = TIMx_CCR2
…
34E2
0000
CC1S = 0b01
CC2S = 0b10
CC1P = 0
CC2P = 1
TIMx_CCR1 = 0x2ED0
TIMx_CCR2 = 0x34E2
IC1 capture
Configuration for the PWM input mode
CC1S bits of TIMx_CCMR1 register select the input for TIMx_CCR1 (TI1)
CC1P bit of TIMx_CCER register selects the active polarity of TI1 (rising edge)
CC2S bits of TIMx_CCMR2 register select the input for TIMx_CCR2 (TI1)
CC2P bit of TIMx_CCER register selects the active polarity of TI1 (falling edge)
TS bits of TIMx_SMCR register select TI1FP1 as trigger for the slave controller
SMS bits of TIMx_SMCR register configure the slave controller in reset mode
CC1E and CCE2 bits of the TIMx_CCER register enable the captures
TIMx - Timer
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TIMx one pulse mode
Generation of a pulse synchronized with an external event
Particular case of the previous modes
Starting the controller can be controlled by the slave mode controller
Generation the waveform can be done in output compare mode
Counter
…
FFFC
0000
0001
0002
2ED0
2ED1
2ED2
0000
TIMx_CCR1 = 0x2ED0
TIMx_ARR = 0x2ED3
CC1P = 0
TI2
OC1
2ED3
CC1P = 1
CC1P = 1
CC1P = 1
Compare 1
Configuration for the one pulse mode
OPM bit of TIMx_CR1 register selects one pulse mode
IC2S bits of TIMx_CCMR1 register maps TI2FP2 on TI2
CC2P bits of TIMx_SMCR register select the rising edge detection for TI2FP2
TS bits of TIMx_SMCR register configure TI2FP2 as trigger for the slave mode controller
SMS bits of TIMx_SMCR register enable TI2FP2 signal to start the counter
TIMx_CCR1 register defines the passive period
TIMx_ARR – TIMx_CCR1 defines the active period
CC1P bit of TIMxCCMR1 register fix the polarity of the active signal
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General purpose timer block diagram
TIM - Timer
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TIM - Timer
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Presaler
The prescaler can divide the counter clock frequency by any factor between 1 &
65536
Itis based on a 16-bit counter controlled through a 16-bit register (TIMx_PSC
register)
Timer Register Map (1/3)
TIM - Timer
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RM0008 Reference manual (page 407)
TIM - Timer
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Timer Register Map (2/3)
Timer Register Map (3/3)
TIM - Timer
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ARM Peripheral Bus 2 access (APB2)
TIM - Timer
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RM0008 Reference manual (page 51)
TIM - Timer
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ARM Peripheral Bus 1 access
(APB0)