Transcript chip - ET
44% 1
5 Packaging Intro
•
Ken Gilleo PhD
•
ET-Trends LLC
Package
2
PROTECTION
MEMS Chip to PCB Compatibility Rerouting Thermal Management Performance Enhancement Reworkability PROTECTION Enable repair Easy Assembly Easy Testability Automated Handling Low Stress Selective Access to Environment Standardization Enable Mechanical Movement
3
Packaging Change Drivers
1.
Miniaturization Area Height Weight
2.
Performance
High lead count High frequency; processors, RF
3. MEMS/MOEMS/Nano
;
a new technology cluster
4
~50 Years Vacuum
Devices
~50 Years Nano MOEMS MEMS Solid State TIME
5
Basic Package Elements
•
Base; platform; chip carrier
•
1 st Level Interconnect (to chip)
•
Routing (can be optional)
•
2 nd Level Interconnect (to substrate/PCB)
•
Enclosure; encapsulant
•
Special features
Thermal management Ports, windows, other
6
Packages Element – cont.
•
Substrate/Platform/Enclosure
Rigid organic; BT, etc.
Flexible organic; polyimide Ceramic/glass Metal with insulation DIELECTRICS Protection; enclosure, encapsulation, passivation
•
Chip Connections (1st level)
Wire bond TAB Integrated TAB DCA; Flip Chip DIE
•
PCB Assembly (2nd level)
Fusible: solder spheres/balls/bumps Non-fusible: leads, pins, pads CONDUCTORS CONDUCTORS
7
Lead Frames
• • • • •
Metal – free standing or pre-inserted into dielectric Framing structure removed later Ceramic hermetic; used for MEMS Plastic Near-hermetic; limited use for MEMS Finishes for die attach/bonding
Ag
Pd Au Ni Multiple
8
Chip Carriers
Chip Carrier: a packaging system for electronic chips (IC’s) that provides protection and a practical means of connecting to circuitry.
Fan Out: 2 nd Level interconnect fans outward from 1 st level Conductor and Dielectric Fan In: First - 1964 A flex-based package
9
Area Array Packages
•
Flip Chip
•
LGA (Land Grid Array); leadless chip carrier, QFN
•
PGA (Pin Grid Array)
•
BGA (Ball Grid Array)
•
Micro-BGA (CSP)
10
Advanced Packaging Types
•
Advanced BGAs
•
Flex-Based
•
MultiChip
•
CSP
•
Array Molded PRODUCTIVITY
•
Wafer-Level CSP and FC
Flip Chip
•
Perimeter for small I/O count
•
Area Array is much more effective
11
MEMS potential Selective underfill MEMS
12 •
Cofired
Ceramic Packages
Used for MEMS Hermetic moderately expensive
•
Cast
•
Molded
•
Open (non-hermetic); chip carrier
13
Organic Substrate
•
Rigid; mostly epoxies (resin-glass)
FR4 conventional
FR4 type non-halogenated
BT (Bismaleimide-triazine)
New non-epoxy halogen-free products
•
Flexible
Polyimide
LCP Limited use for MEMS Non-hermetic Lowest cost
MultiChip Packages
Traditional Stacked Single-Plane Cavity type used MEMS + ASIC, other
14
Infineon MEMS mic + ASIC chip
15
Packaging Steps
•
Bond die (chip) to base; die attach)
•
1 st Level connect chip; wire bonding
•
Enclosure; encapsulant
16
Wire Bonding (WB)
•
Most common connection
•
Gold ball bonding dominants (~ 93%)
•
Features
Programmable; handles die and package change
Very versatile
Universal method Fast, automatic, equipment makers keeping pace Fully mechanical process Clean; no pollution, waste, hazardous materials Well-suited for MEMS/MOEMS
17
Package Protection
•
Fabricated cavity enclosure ; metal, plastic, ceramic
•
Transfer Molding Compounds (solids)
•
Glob Top; free flow encapsulant DIE
•
Dam & Fill encapsulants
•
Cavity fill encapsulants
•
Underfill; 4 basic classes
•
Underfill + encapsulant
•
Injection molded cavity packages; near-hermetic
18
encapsulants:
BGA
for protection & handling DIE Only suitable for capped MEMS CAP MEMS
19
Session Summary
•
Packaging is very dynamic today
•
The package is all about metal & dielectrics
•
Challenges are greater than ever
•
Chip advances push performance
•
WLP is finally gathering momentum
•
MEMS is opening up a new packaging industry