Transcript 2 - rt2010_hf

A scalable DAQ system using
the DRS4 sampling chip
H.Friederich1, G.Davatz1, U.Hartmann2, A.Howard1,
H.Meyer1, D.Murer1, S.Ritt2, N.Schlumpf2
1 ETH Zurich, Switzerland
2 Paul Scherrer Institute, Switzerland
Outline
1. Introduction
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WaveDREAM Project
DRS4 Chip
2. Realization
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Analog Frontend
Continuous Digitization
Digital Backend
3. Results
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System Bandwidth
Noise Power Spectrum
System Nonlinearity
Hannes Friederich – May 2010
Slide 2
WaveDREAM Project
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Motivation: 1 GSPS, 8-bit, low cost,
multichannel system for pulse shape
discrimination and photon counting
Development of a flexible DAQ system
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Based on the DRS4 chip
Active amplification
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20 dB gain
≥ 500 MHz bandwidth
Scalable no. of channels
Optimized for small amplitude (~10 mV), high frequency
signals (~1 GHz), e.g. PMT
Capability for 1 ns global event timestamps
Digital Trigger (FPGA)
General purpose board
Hannes Friederich – May 2010
Slide 3
DRS4 Chip (Developed at PSI)
FUNCTIONAL BLOCK DIAGRAM
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Stores the analog waveform
 up to 5 GSPS
 11.5 bit SNR
Slower SCA readout
 Less expensive ADC electronics
 Region of interest readout
 NumberOfBins x 30 ns
PLL
WSRIN
DENABLE
DWRITE
REFCLK
DTAP A0 A1 A2 A3
LVDS
DOMINO WAVE CIRCUIT
IN0
MUX
CHANNEL 0
OUT0
CHANNEL 1
OUT1
CHANNEL 2
OUT2
CHANNEL 3
OUT3
CHANNEL 4
OUT4
CHANNEL 5
OUT5
CHANNEL 6
OUT6
IN7
CHANNEL 7
OUT7
IN8
CHANNEL 8
IN1
IN2
IN3
IN4
IN5
IN6
WRITE SHIFT REGISTER
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AGND AVDD DSPEED PLLOUT PLLLCK
ENABLE
Large Switched Capacitor Array
(SCA)
WRITE CONFIG REGISTER
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OUT8/
MUXOUT
O-OFS
BIAS
ROFS
SROUT
WSROUT
STOP SHIFT REGISTER
RSRLOAD
SRIN
SRCLK
READ SHIFT REGISTER
MUX
RESET
CONFIG REGISTER
DVDD DGND
8+1 channels
Individual Channel depth 1024 bins
Channel cascading
Parallel or serial channel readout
Hannes Friederich – May 2010
Slide 4
DRS4 Transparent Mode
Input directly accessible at output while
recording
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50 MHz Bandwidth
Continuous sampling of the input
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Same ADC as DRS readout
Digital trigger
Arbitrary event record length
Eliminates the need for splitting the signal at the
frontend
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Reduces PCB complexity
Transparent Mode gain:
½ of SCA gain
SCA
Hannes Friederich – May 2010
MUX
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LP
Slide 5
Design Realization
Analog Frontend
Digital Trigger in the FPGA
(e.g. Threshold, CFD)
DRS4
ADC
Board-to-board
communication
FPGA
Readout of all 8 pipelines in parallel
Minimizes DRS4 dead time
Gigabit
Ethernet
UDP
connection
to backend
Board-to-board
communication
Hannes Friederich – May 2010
Slide 6
Analog Frontend
DAC
THS
4508
DRS4
50
THS
4302
50
50
baseline DC offset
+ 14 dB
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+ 6 dB
AC coupled input
Fixed gain 20 dB
Adjustable baseline
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Accommodates all signal polarities
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Input remains in linear range of DRS4
Input span: 1 V p-p
Input levels between
0.1 and 1.5 V
Frontend-only bandwidth > 1 GHz
Hannes Friederich – May 2010
Slide 7
Continuous Digitization
AD9212
CLK
DRS4
FPGA
AD9212
Sample Modes:
- Continuous
sampling
(120 MSPS)
- DRS Readout
(30 MSPS)
Trigger
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AD9212: 8 Channel, 10 bit ADC, 65 MSPS
Transparent Mode: 50 MHz bandwidth
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Sampling theorem: ≥ 100 MSPS or additional low-pass
filtering
More bandwidth increases SNR for high-frequency pulses
Solution: 2 AD9212 with 180 degrees clock phase
shift, 120 MSPS
Hannes Friederich – May 2010
Slide 8
Global Timestamps
DRS4
FPGA
LP
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Global Clock & Reference signal distributed to all boards
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Avoids clock skew
Use clock conditioner chips to reduce clock jitter
Sample the reference signal in the DRS4 to extract fine-grain
timestamps
Calibrate propagation delays
Not tested – No numbers
Hannes Friederich – May 2010
Slide 9
Prototype Implementation
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Mezzanine Card
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Analog electronics, DRS4 chip, ADCs
Carrier Card
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Slots for 2 mezzanine cards
2 FPGAs (Xilinx Spartan 3A)
Communication Layer
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Gigabit Ethernet
 UDP / IP / MAC layer in VHDL
Board-to-board communication
 960 Mbit/s
USB 2.0
RS-485
VME form factor (6U)
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Provides mechanical support,
power supply & cooling
No support for VME bus
Hannes Friederich – May 2010
Slide 10
Results: System Bandwidth
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Input capacitance of DRS limits bandwidth
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500 MHz Bandwidth
Nonlinear amplification around 300 MHz
Hannes Friederich – May 2010
Slide 11
Transparent Mode Bandwidth
Bandwidth [-3dB]: 60 MHz
Hannes Friederich – May 2010
Slide 12
Noise Power Spectral Density
DRS Readout (1.024 GSPS)
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ENOB 8 – 8.5 bit
Hannes Friederich – May 2010
Slide 13
Baseline Adjustment
ADC range [0 1024]
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Baseline can be adjusted
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Linear adjustment circuit
Hannes Friederich – May 2010
Slide 14
Amplitude Nonlinearity
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Amplitude Nonlinearity less than 1 ADC value
Hannes Friederich – May 2010
Slide 15
Applications
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A performant system has been demonstrated
Possible applications include
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Pulse shape discrimination
Photon counting from PMTs
Oscilloscope functionality
Arbitrarily flexible trigger logic in the digital domain
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Window coincidence already implemented
If you’re interested in using the WaveDREAM board,
please contact me afterwards
Hannes Friederich – May 2010
Slide 16
PMT Signals
First part of
transparent mode
signal equals DRS
readout signal
Hannes Friederich – May 2010
Slide 17
Conclusion
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A challenging design realized
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Good bandwidth achieved (500 MHz)
Region of interest sampling up to 5 GSPS
120 MSPS continuous sampling
 Digital Trigger logic
ENOB 8 - 8.5 bit
Gigabit Ethernet
Cost Effective
Flexible design for multiple applications
Thanks to Arktis Radiation Detectors Ltd & CTI for
financial support
Hannes Friederich – May 2010
Slide 18
Hannes Friederich – May 2010
Slide 19