Transcript PLAyer: A Tool for Fast Mapping of Combinational Logic for Design

Faster Logic Manipulation
for Large Designs
Alan Mishchenko
Robert Brayton
University of California, Berkeley
Outline
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Motivation
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Choosing the canonical form
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Historic viewpoint
Disjoint-support decomposition (DSD)
DSD manager
Impact on computations
Experimental results
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Simple, local, iterative computation
Millions of 6-16 input functions (“small practical functions” = SPFs)
Runtime / memory / quality can be improved
Statistics of DSD functions
Runtime improvements
Typical DSD structures
Conclusions
2
Disjoint Support Decomposition
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Primitive gates
Const0
 AND
 XOR
 PRIME
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MUX
 Majority
d
a
b
e
c
 2:1
f
g
h
i
k
3
References
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Canonical form
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Computation from cofactors
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T. Sasao and M. Matsuura, "DECOMPOS: An integrated system for functional
decomposition," Proc. IWLS ’98, pp. 471-477.
S.-I. Minato and G. De Micheli, “Finding all simple disjunctive decompositions
using irredundant sum-of-products forms”. Proc. ICCAD’98, pp. 111-117.
Boolean operations
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Y. Matsunaga, "An exact and efficient algorithm for disjunctive decomposition",
Proc. SASIMI '98, pp. 44-50.
Alternative computations
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V. Bertacco and M. Damiani, "Disjunctive decomposition of logic functions,"
Proc. ICCAD ‘97, pp. 78-82.
Computation from cofactors (corrections)
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R. L. Ashenhurst, “The decomposition of switching functions”. Computation
Lab, Harvard University, 1959, Vol. 29, pp. 74-116.
S. Plaza and V. Bertacco, "Boolean operations on decomposed functions",
Proc. IWLS ’05.
Applications in synthesis and mapping
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A. Mishchenko, R. K. Brayton, and S. Chatterjee, "Boolean factoring and
decomposition of logic networks", Proc. ICCAD'08, pp. 38-44.
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Timeline of (Canonical) Forms
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Truth tables (TTs) (< 1980)
Sums-of-products (SOPs) (1980-1990)
Binary decision diagrams (BDDs) (1990-2000)
And-inverter graphs (AIGs) and truth tables (2000-2012)
Disjoint-support decompositions (DSDs) (> 2012)
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For small practical functions (SPFs) only
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DSDs vs BDDs vs TTs for SPFs
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TTs dominate BDDs in terms of memory and runtime
TTs and BDDs are equally (in)convenient for detecting
Boolean properties
DSDs take less memory/runtime than BDDs/TTs for
pratical functions of K inputs (8 < K < 16)
DSDs explicitly represent Boolean properties
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Symmetry, unateness, NPN canonicity, decomposability, etc
Very important for practical applications!
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DSD Manager
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Similar to BDD manager
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Maintains canonical forms
Performs Boolean operations
Employs computed table
Different from BDD manager
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Different data structure
Different normalization rules
More reusable computed table
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Primitives of DSD Manager
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One constant 0 node
One primary input node n
Multi-input AND and XOR nodes with ordered fanins
Three-input MUX nodes
Multi-input PRIME nodes
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Non-decomposable functions
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Canonicity of DSDs
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Propagating inverters
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Collapsing operators
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AND(a, AND(b, !AND(c, d))  AND(n, n, !AND(n, n))
Ordering fanins of AND/XOR
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AND(!a, !XOR(b, c))  AND(n, XOR(n, n))
Use support size
If there is a tie, AND precedes XOR precedes MUX precedes PRIME.
If there is a tie, a non-inverted fanin precedes a inverted fanin.
If there is a tie, the fanins’ fanins are ordered and compared in their
selected order
If the recursive comparison fails to produce a unique order, the fanins’
DSD structures are isomorphic and therefore their order is immaterial.
Unifying variables
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AND(a, XOR(b, c), MUX(d, e, f))  AND(n, XOR(n, n), MUX(n, n, n))
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Boolean Properties of SPFs
(industrial benchmarks)
% of functions and classes
Cut size
6
8
10
12
14
Cuts
30037253
33637730
35044059
35641114
35910126
Funcs
0.88
2.25
3.09
3.73
4.20
NPNs
0.04
0.24
0.59
0.97
1.26
% of functions and classes
Cut size
6
8
10
12
14
Cuts
30037253
33637730
35044059
35641114
35910126
Funcs
0.88
2.25
3.09
3.73
4.20
NPNs
0.04
0.24
0.59
0.97
1.26
% of DSDs relative to NPN
classes
Full
6.15
10.91
17.40
21.03
22.02
1-step
64.32
58.42
49.96
42.08
36.86
Complex
29.53
30.67
32.64
36.89
41.12
% of DSDs relative to the
number of cuts
Full
93.16
86.28
80.78
75.06
71.06
1-step
6.24
11.07
14.22
16.87
17.71
Complex
0.60
2.65
5.00
8.07
11.23
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Boolean Properties of SPFs
(public benchmarks)
% of functions and classes
Cut size
6
8
10
12
14
Cuts
19854401
21167936
21340473
21766880
22002227
Funcs
1.68
4.66
6.71
7.92
8.89
NPNs
0.07
0.56
1.46
2.23
2.92
% of functions and classes
Cut size
6
8
10
12
14
Cuts
19854401
21167936
21340473
21766880
22002227
Funcs
1.68
4.66
6.71
7.92
8.89
NPNs
0.07
0.56
1.46
2.23
2.92
% of DSDs relative to NPN
classes
Full
4.74
8.27
11.57
12.55
11.99
1-step
58.38
47.22
37.79
32.69
28.40
Complex
36.88
44.51
50.63
54.76
59.61
% of DSDs relative to the
number of cuts
Full
89.72
78.48
69.96
63.51
60.36
1-step
9.32
16.36
19.60
20.93
19.25
Complex
0.96
5.16
10.44
15.56
20.39
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LUT Structure Mapping Runtime
Name
i10
pj1
aqua
Geo
PI
257
1769
1941
PO
224
1063
4805
AND
2675
16285
25058
Match (TT), sec
9.44
54.37
122.23
1.000
Total (TT), sec
14.13
82.69
169.67
1.000
Name
i10
pj1
aqua
Geo
PI
257
1769
1941
PO
224
1063
4805
AND
2675
16285
25058
Match (DSD), sec
0.21
2.19
4.05
0.031
Total (DSD), sec
2.41
11.52
22.85
0.147
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Typical DSD Structures
2 inputs
(ab)
[ab]
3 inputs
(abc)
(a!(bc))
[abc]
[a(bc)]
(a[bc])
<abc>
4 inputs
(abcd)
(a!(b!(cd)))
[abcd]
(a[b(cd)])
(a<bcd>)
<ab[cd]>
5 inputs
(abcde)
(a[(bc)(de)])
(a!(!(bc)!(de))
(a<b(cd)e>)
<a(bc)(de)>
<a<bc!(de)>>
6 inputs
(abcdef)
(ab[(cd)(ef)])
(!(abc)!(def))
[a<b[cd][ef]>]
<a(bc)<def>>
<(ab!(cd))ef>
!a = NOT( a )
(ab) = AND( a, b )
[ab] = XOR( a, b )
<abc> = MUX( a , b , c )
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Conclusion
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(Re)invented DSD
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Canonical form, which exposes Boolean properties
Introduced a DSD package
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An alternative to a BDD package for SPFs
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Discussed preliminary experimental results
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Exciting future work is waiting to be done!
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Abstract
When logic transformations, such as circuit restructuring, technology
mapping, and post-mapping optimization, are repeatedly applied to
large hardware designs, millions of relatively small (6-16 input)
Boolean functions have to be efficiently manipulated. This paper
focuses on a novel representation of these small functions, in terms
of their disjoint-support decomposition (DSD) structures. A new
DSD manipulation package is developed, which allows for faster
logic manipulation compared to known methods.
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