Transcript ISD S.A. Very High Resolution DAC for Space Applications

AMICSA 2010
Validation Results of a
Radiation Hardened
24-bit Digital-toAnalogue Converter
K. Makris1, D. Fragopoulos1, G. Tsiligiannis1, T. Lambaounas1,
P. Anagnostopoulos1, C. Papadas1, J.P. Schoellkopf 2, B. Glass3
(1)
(2)
(3)
Integrated Systems Development (ISD S.A.), Athens, GREECE
Advanced System Technology and User Service (ASTUS S.A.), Grenoble, FRANCE
European Space Research and Technology Center (ESA/ESTEC) – Microelectronics Section
(TEC-EDM), Noordwijk, THE NETHERLANDS
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Overview
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Features
Architecture
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Layout – chip fabrication
Package
Validation plan overview
Validation board and test setup
Electrical test results
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Digital part
Analog part
Static performance summary
Dynamic performance summary
Radiation tests and setup
Radiation test results
Conclusions and future work
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Product highlights
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Features
 Architecture: multi-bit ΣΔ modulator
 Output stage: differential current steering
 Digital input interface: Synchronous serial data format
 Bandwidth: 0.1mHz – 1kHz
 Sampling frequency: selectable 6kHz or 12 kHz
 Oversampling ratio: selectable x256 or x128
 Configuration via I2C interface
 1.2V digital power supply
 3.3V analog power supply
 Radiation tolerant design
Operating modes
 Normal
 Bypass
 Test
 Power down 1  Digital ON / Current sources OFF / Reference block ON
 Power down 2  Digital ON / Current sources OFF / Reference block OFF
Applications
 High accuracy instrumentation and actuator drive for systems operating in space
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System Overview
DAC24BISDA
1.2V
SDA
SCL
MCLK
Input
interface
I2C
interface
Interpolation
stage
3rd order
ΣΔ
modulator
Clock
Distribution
network
DWA
Test
signals
OUTP1
DAC 1
(Main)
Level Shifters (1.2 - 3.3V)
SDIN
SCLK
SYNC
3.3V
Reference
block
OUTM1
Ref.
Voltage
OUTP2
DAC 2
(Redunda
nt)
OUTM2
DFT
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Architecture: Digital Part (1/2)
1.2V
Clock
Distribution
network
SDIN
SCLK
SYNC
IRP1
Linear
Phase X2
Digital
input
interface
IRP2
Halfband
X2
IRP3
Halfband
X2
Interpolator
I2C
Registers
bank
Write
SDA
SCL
3rd order
ΣΔ
Modulator
Read
I2C
interface
Test
signals
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DFT
block
DWA
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DATAp1 [31:0]
SINC
X32/X16
Digital to Analog interface block
(Level Shifters)
MCLK
DATAm1 [31:0]
CLK1
PDN_ANA
DATAp2 [31:0]
DATAm2 [31:0]
CLK2
DATA [31:0]
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Architecture: Digital part (2/2)
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Modulator design
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3rd order feed-forward ΣΔ modulator
5-bit quantizer
Sampling frequency 6kHz when OSR
X256 and 12kHz when OSR X128
Idle Tone avoidance by introduction of
dither
Dynamic Element Matching (DEM)
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The output element mismatch error is
minimized by the use of a DEM algorithm.
Data Weighted Averaging (DWA) as an
efficient DEM algorithm.
Algorithm's objective → achieve an equal
use of elements in long-term by rotating
the output elements (current sources) in a
cyclic fashion.
DWA uses only one index, which is
updated with the addition of the input
every clock cycle.
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Architecture: Analog Part
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Bandgap cell provides an accurate reference voltage (1.2V) with a low temperature coefficient.
First order RC filter reduces any noise from the bandgap block.
Low noise Op-Amp along with M1 and current setting resistor (Rref or Rext) implements the reference
current source for generating the reference current I ref.
IRef can be set by selecting the internal resistor RRef or connecting an external resistor Rext.
Differential elementary current sources built around the regulated cascode topology.
Use of PMOS transistors for lower flicker noise(1/f) and high linearity.
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Radiation hardening techniques
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Technology level: ST Microelectronics HCMOS9 0.13 um is a rad-hard proven
technology.
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Library level: For the digital part the most oversized and robust standard cells
were used (including latches and flip-flops).
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Digital design level
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Analogue design level
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Fault masking by TMR (e.g. FSMs)
Synchronous reset
Reset assertion in the SINC block every 32 clock cycles
Current source transistors with increased W/L ratio for increased capacitance
and driving power.
Layout level
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Deep N-well isolation (NISO): The entire digital part and all the NMOS devices of
the analogue part are placed inside a deep n-well to minimize digital feedthrough and latch-up susceptibility (see slide 10).
 P+ guard rings surround the n-channel devices to cut any possible radiation
induced parasitic paths.
 Increased distance between the p+ diffusion in the well and the n+ in the
substrate.
 Increased number of substrate and well contacts.
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Floor-plan and fabrication
highlights
Polarization
block
Analog
ring
Current sources
matrix
1840 um
48-lead hermetically sealed
ceramic flat package
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Technology: 0.13um HCMOS9-GP
ST-MicroelectronicsTM 6 metal layers
Line name: DAC24BISDA
Dimensions: ~ 1840 x 1840 um
Total area: 3.42mm2
No of I/O pads: 43
Minimum pad-to-pad spacing: 90um
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1840 um
Digital ring
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Digital
core
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Process
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Deep N-Well isolation (NISO)
 Minimizes the digital feed-through to the
sensitive analog nodes
 Improves the latch-up immunity
Layout and polarization scheme:
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Package
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48 lead hermetically sealed ceramic flat package
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Well proven space reliability (ST products)
External dimensions: (E1 x D) 9.65 x 15.72mm
Die attach cavity dimensions: (L x W) 5.58 x 3.55mm
Bonding pad cavity dimensions: (L x W) 8.50 x 5.46
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Validation plan overview
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Functional and performance validation - characterization
Static performance tests
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DAC24BISDA
validation
Dynamic performance tests
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INL, DNL
Offset and gain errors
Power consumption
Output current levels
THD+N
SNR, ENOB
Dynamic range
Performance
Radiation sensitivity tests
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Functional
SEE → SEU, SEL
TID
Device
Characterization
Radiation tests
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Validation board
System block diagram
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Modular architecture --> Motherboard + DUT
daughterboard
FPGA based design
Memories
UART and USART interfaces
Dedicated power supplies for the DUT
On-board ADC and footprint for a second
DAC for performing the SEU tests.
FLASH memory
DUT
Power
Supply
domains
Remote
keypad
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DAC
Outputs (SMA)
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DAC DUT
ADC
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Generic test setup
POWER
SUPPLY
DAC validation board
1.2V
3.3V
SCLK
OUTP (1/2)
CH1
SYNC
FPGA
SDIN
ARST
DAC24BISDA
SCL
CH2
SDA
OUTM (1/2)
RL
MCLK
CL
CLOCK
GENERATOR
RL
Spectrum analyzer
/ Oscilloscope
CL
AGND
PERSONAL
COMPUTER
MATLAB®
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Validation results: Test conditions
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Unless otherwise noted, the following test conditions apply
for all the tests:
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Minimum: Digital power supplies VD=1.08V and analog power
supplies VA=3.0V
Typical: VD=1.2V and VA=3.3V
Maximum: VD=1.25V and VA=3.6V
Ambient temperature: Ta=25ºC
Internal reference current setting resistor Rref=219 Ω
fMCLK=1.536 MHz
OSR x 256 (fs=6 kHz)
Output load: resistive 100 Ω (1% tol.) // 300 pF ceramic capacitor.
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Static electrical parameters summary
Parameter
Description
Value
Unit
VD
Digital supply voltage
1.2 (typ)
V
VA
Analog supply voltage
3.3 (typ)
V
PD
Digital power consumption
1.52 (typ)
mW
PA
Analog power consumption (normal mode)
65.3 (typ)*
mW
Pt=PA+PD
Total power consumption (normal mode)
66.8 (typ)
mW
Ptdwn2
Total power consumption (Power down 2
mode)
2.41 (typ)
mW
VBGOUT
Internal reference voltage
1.193
V
Io
Differential output current
(per DAC)
5.83
mA
ICM
Common mode output current
2.90
mA
ILSB
Output current steered by a single CS
182
uA
Offset error
11
uA
INL
Integral non-linearity
0.5
LSB
DNL
Differential non-linearity
0.5
LSB
e(offset)
(*) It is possible to reduce the analog power consumption by using a higher external current setting resistor Rext.
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Time domain waveform
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Differential output DAC1, normal mode, sine wave 100Hz -1dBFS
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Dynamic electrical parameter summary
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Normal Mode, sine 100 Hz / -3 dBFS, MBW=1kHz, unbalanced output
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Results
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Dynamic range (DR):
113 dB
 THD+N (SINAD):
108dB
110 dB
‘bulge’ due to
insufficient data
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Radiation tests
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Preliminary radiation tests include TID and SEE (SEU, SEL)
Up to now only TID testing has been performed
TID test location: Co-60 source at ESA-ESTEC, The Netherlands
Dose rate setting by adjusting the distance between the DUT and the source (X)
TID test setup overview
X
DUT
Co60
source
Radiation chamber
Data
logger
PSU
C0-60 facility at ESA-ESTEC
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Radiation test results summary
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TID testing
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DUT sample setup
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Monitored parameters
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OUTP1, OUTM1, OUTP2, OUTM2, VPOL, VBGOUT, IA, ID
Radiation parameters
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Under bias conditions
Constant sourcing of maximum output current (both DAC ON)
Constant dose rate: 85.4 Rad/min
Total accumulated dose: 111.4 kRad (H20) approx. 100 kRad (Si)
Data recording sampling rate: 1 measurement / min
Results
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No change in the value of the monitored parameters through the duration of the test.
No abnormal operation observed
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Conclusions and future work
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The cut 2.0 has been released in order to:
 include
some enhancements in the digital part (serial
input interface, register triplication)
 deduce derivatives (100Ksamples and 1 Msamples)
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Perform a detailed SEU and SEL analysis
The part is included in the catalog of STMicroelectronics for space application products
Qualification for use in space will follow.
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Thank you for your attention!
Questions?
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