Transcript Workshop Slides

Tools for Discovery
Digital Pulse Processing Workshop
September 22nd 2010, GSI
Carlo Tintori
Outline
•
Description of the hardware of the waveform digitizers
•
Use of the digitizers for physics applications
•
Comparison between the traditional analog acquisition chains and the new fully
digital approach
•
DPP algorithms:
• Pulse triggering
• Zero suppression
• Pulse Height Analysis
• Charge Integration
• Gamma-Neutron discrimination
• Time measurement
• Multi Channel Scaler
•
Overview on the CAEN Digitizer family
•
Experimental setup description and practical demonstrations
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Digitizers vs Oscilloscopes
• The principle of operation of a waveform digitizer is the same as the
digital oscilloscope: when the trigger occurs, a certain number of
samples (acquisition window) is saved into one memory buffer
• However, there are important differences:
–
–
–
–
no dead-time between triggers (Multi Event Memory)
multi-board synchronization for system scalability
high bandwidth data readout links
on-line data processing (FPGA or DSP)
M e m o ry B u ffe r
T IM E S T A M P
S [0 ]
S [1 ]
S [2 ]
S [3 ]
A C Q U IS ITIO N W IN D O W
S [n -1 ]
Sam pling C lock
TR IG G ER
Tim e
PR E
PO ST TR IG G ER
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Block Diagram
• Mother-daughter board configuration:
•
The mother board defines the form-factor; it contains one FPGA for the readout
interfaces and the services (power supplies, clocks, I/Os, etc…)
•
The daughter board defines the type of digitizer; it contains the input amplifiers,
the ADCs, the FPGA for the data processing and the memories
DAUG THER BO ARDS
M O THER BO ARD
C L K -O U T
C L K -IN
S A M P L IN G C L O C K
PLL
F IX E D G A IN
A M P L IF IE R
ANALOG
IN P U T s
IN T . O S C IL L .
+
ADC
V M E /U S B
LO C AL BU S
FPGA
(A M C )
DAC
G LO BAL TR G
SYNC
FPGA
(V M E )
CONET
SELF TR G
T R G -IN
n C H AN N ELS
S Y N C -IN
SRAM
MEMORY
T R G -O U T
I/O s
DAC
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M O N IT O R
Board Layout
Opt. Link
I/Os
TRG in-out
DAC out
CLK in-out
ADC
PLL
FPGA
FPGA
Lin. Reg.
LOCAL BUS
DC-DC
DC-DC
Memory
VME
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Multi-board synchronization (I)
• Clock distribution
• External Clock In/Out (differential LVDS)
• Clock Distribution:
• Daisy Chain: Clock-Out to Clock-In chain (the first board can act as a clock master)
• Fan-Out: one clock source + 1 to N fan-out
• High performance and low jitter PLL for clock synthesis
• Frequency multiplication: necessary when the sampling clock frequency is high
• Jitter cleaning: the PLL can reduce the jitter coming from the external clock source
• Programmable clock phase adjust to compensate the cable delay
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Multi-board synchronization (II)
• Trigger and Sync Distribution
• External Trigger In/Out plus 16 PIOs(*) for individual trigger propagation
• Trigger Time Stamp synchronous with the ADC sampling clock
• External Sync input to start-stop the acquisition synchronously and/or to
keep the time stamp alignment between boards
• External Trigger and Sync must be synchronous with the sampling clock,
otherwise the re-synchronization causes a one clock period jitter between the
boards
• The trigger in-out daisy chain can be used to distribute both trigger and sync
synchronously with the sampling clock
• In any case, when the trigger represents also a precise time reference, it is
necessary to digitize it using one channel
• The trigger latency can be compensated by means of the pre-trigger size
(memory look back)
(*) VME boards only
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Triggers and acquisition
•
Trigger types:
• External Trigger (same as the ‘Ext Trigger’ in the scopes)
• Software Trigger (same as the ‘Auto Trigger’ in the scopes)
• Self-Trigger (same as the ‘Normal Trigger’ in the scopes)
•
The trigger can be common to all the channels in a board (like in the scopes) or
individual
•
Self trigger: just a digital comparator (voltage threshold) or advanced triggers
based on algorithms implemented in the FPGAs (input pulse recognition)
•
Programmable Acquisition Window and Pre/Post Trigger Size
•
Dead-Timeless Multi Event Acquisition (memory paging)
•
VME digitizers can use the digital I/Os to send and receive the individual selftriggers to an external logic unit (like the V1495) to make coincidences,
multiplicity, neighbour trigging, etc…
•
Individual trigger propagation and coincidence is used for segmented germanium
detectors, silicon strip detectors, wire chambers, PET, etc…
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Fundamentals of A/D conversion
•
Analog Bandwidth <= Sampling rate / 2
•
LSB = Dynamic Range / 2Nbit
•
Quantization noise:  = LSB / 12 = ~ 0.3 LSB
•
SNR = 20 log (S/N); THD = 20 log (S/D); SINAD = 20 log (S / (N+D))
•
Effective Number of bits: ENOB = (SINAD – 1.76dB) / 6.02
•
Oversampling: Fovs = 4 Nadd
•
Sampling clock jitter: SNRJITTER = -20 log (2 FANALOG TJITTER)
•
Other sources of noise: DNL, INL
*
Fs  N’bit = Nbit + NAdd
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Digitizers for Physics Applications
• Traditionally, the acquisition chains for radiation detectors are made out
of mainly analog circuits; the A to D conversion is performed at the very
end of the chain
• Nowadays, the availability of very fast and high precision flash ADCs
permits to design acquisition systems in which the A to D conversion
occurs as close as possible to the detector
• In theory, this is an ideal acquisition system (information lossless)
• The data throughput is extremely high: it is no possible to
transfer row data to the computers and make the analysis offline!
• On-line digital data processing in needed to extract only the information
of interest (Zero Suppression & Digital Pulse Processing)
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Traditional chain: example 1
charge sensitive preamplifiers
T IM E
Q = ENERGY
DETECTOR
D E C A Y T IM E
R IS E T IM E
P R E A M P L IF IE R
P E A K A M P L IT U D E = E N E R G Y
S H A P IN G A M P L IF IE R
T IM IN G A M P L IF IE R
Z E R O C R O S S IN G
CFD
T h is d e la y d o e sn ’t d e p e n d
o n th e p u lse a m p litu d e
CFD OUTPUT
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Traditional chain: example 2
trans-impedance (current sensitive) preamplifier
T IM E
Q = ENERGY
DETECTOR
•
Z E R O C R O S S IN G
CFD
•
GATE
The QDC is not self-triggering; need a
gate generator
need delay lines to compensate the
delay of the gate logic
D E L A Y E D S IG N A L
CHARGE
IN T E G R A T IO N
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Benefits of the digital approach
• One single board can do the job of several analog modules
• Full information preserved
• Reduction in size, cabling, power consumption and cost per
channel
• High reliability and reproducibility
• Flexibility (different digital algorithms can be designed and
loaded at any time into the same hardware)
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Readout Bandwidth
• Example with Mod720:
• 1 sample = 12 bit = 1.5 byte
• 1 channel = 1.5 byte @ 250MHz = 375 MB/s
• 1 VME board = 8 channels = 3 GB/s !!!
• Continuous acquisition not possible!
• Example2 (triggered acquisition):
• Record length = 512 samples (~ 2 s) = 768 bytes per channel
• Trigger Rate = 10 KHz
• 1 VME board = ~ 61 MB/s
• Readout Bandwidth of CAEN digitizers:
•
•
•
•
VME with MBLT:
VME with 2eSST:
Optical Link:
USB 2.0:
60 MB/s
150 MB/s
70 MB/s
30 MB/s
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Digital Pulse detection (self-triggering)
• A good trigger is the basis for both the DPP and the Zero
Suppression
• The aim of the self-trigger is to identify the good pulses and
trigger the acquisition on channel by channel basis
• Pulse identification can be difficult because of the noise,
baseline fluctuation, pile-up, fast repetition, etc…
• Trigger algorithms based on a fixed voltage threshold are
not suitable for most physics applications
• It is necessary to apply digital filters able to reject the
noise, cancel the baseline and to do shape and timing
analysis
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DPP algorithms for triggering
• Timing filter RC-(CR)N:
• High frequency noise rejection (RC filter  mean)
• Baseline restoration (CR or CR2 filter  1st or 2nd derivative) to reduce the
pile-up and low frequency noise effects
• Bipolar signal  Zero crossing time-stamp (digital CFD)
• Constraints on the Time Over Threshold and/or Zero Crossing
can be added to improve the noise rejection
M is s e d P u ls e
B a d T rig g e r
T h re s h o ld
In p u t S ig n a l
T rig g e r
T im e
T h re s h o ld
T im in g
F ilte r
T rig g e r
T im e
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DPP for the Zero Suppression
• Data reduction algorithms can be developed to reduce the data
throughput:
– Full event suppression: one event (acquisition window) is
discarded if no pulse is detected inside the window
– Zero Length Encoding: only the parts exceeding the threshold
(plus a certain number of samples before and after) are saved.
Z L E th re sh o ld
su p p re sse d
L o o k B a ck
W in d o w
su p p re sse d
R e g io n o f
In te re st
su p p re sse d
Look Ahead
W in d o w
T
SAM PLES
T
SAM PLES
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T
SAM PLES
DPP for the Pulse Height Analysis
(DPP-TF)
• Digital implementation of the shaping amplifier + peak sensing ADC
(Multi-Channel Analyzer)
• Implemented in the 14 bit, 100MSps digitizers (mod. 724)
• Use of trapezoidal filters to shape the long tail exponential pulses
• Pile-up rejection, Baseline restoration, ballistic deficit correction
• High counting rate, very low dead time
• Energy and timing information can be combined
• Best suited for high resolution spectroscopy (especially Germanium
detectors)
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DPP-TF Block Diagram
Thr
a b N
ARM ED
COMP
T R G & T IM IN G
F ILT E R
D
R C -(C R )
N
C LK
COUNTER
T IM E S T A M P
T R IG G E R
COMP
ZERO
Nsbl
N = 1 ,2
IN P U T
D E C IM A T O R
ftd
k m M
Nspk
B A S E LIN E
M EAN
D = 1,2 ,4,8
T R A P E Z O ID A L
F ILT E R
PEAK
M EAN
SUB
ftd = F la t T o p D e la y
(b a llis tic d e fic it)
N spk = P eak m ean
M = T im e C o n s ta n t
(P Z c a n c e lla tio n )
T h r = T R G T h re s h o ld
K = S h a p in g T im e
b = R is e T im e
T IM IN G
F IL T E R
T R A P E Z O ID
ze ro cro ssin g
N s b l = B a s e lin e M e a n
ENERGY
m = F la t T o p
a = Low P ass m ean
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DPP-TF / Analog Chain set-ups
N1470
High
Voltage
Ge / Si
N968
N957
Shaping
Amplifier
Peak
Sensing ADC
Energy
C.S.
PRE
DT5724
14bit @ 100MSps
Digitizer + DPP-TF
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Energy
Time
DPP-TF vs Analog Chain
• PROs
–
–
–
–
–
–
–
–
–
–
All in one board
Stability and reproducibility
Flexibility (FPGA based algorithms)
Counting rate (low dead-time)
Ballistic deficit correction
Timing information
Wide Dynamic Range
Channel density
Synchronization and coincidences in multiple channel systems
Total Cost per Channel
• CONs
– Parameters set-up (need good software interface)
– Getting started more difficult
Energy Resolution? Better or worse depending on the conditions
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DPP-TF: Test Results
•
Germanium Detectors at LNL (Legnaro - Italy) in Nov-08 and Feb-09, at GSI (Germany)
on May-09, at INFN-MI on Jan-10, in Japan on Feb-10, at Duke University (USA) on Jul10; resolution = 2.2 KeV @ 1.33 MeV (60Co)
•
Silicon Strip (SSSSD and DSSSD) and CsI detectors in Sweden at Lund and Uppsala (ion
beam test)
•
NaI detectors in CAEN (see demo)
•
PET in U.S.A.
•
Homeland security application using CsI
•
BGO detector at ENEA ‘Centro Ricerche Casaccia’ (Rome)
60Co with
228Th with
DSSSD
Ge
FWHM @ 1.33 MeV:
2.2 KeV
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DPP for Segmented and Strip Detectors
• Same algorithms implemented in the DPP-TF (trapezoidal filters)
• Being implemented in the 14 bit, 100MSps digitizers (mod. V1724)
• Neighbour channels trigger logic: it must be possible to propagate the
local trigger of any channel to any other channel, either within the
board or from board to board
• Use of the GPIO[15:0] connected to a V1495 (general purpose
programmable trigger unit)
• Triggered channel save an event made of Time Stamp, Energy and a
short piece of Waveform (the rising edge, typically a few tens of
samples)
• The memory buffers are used to pack many small events in order to
increase the readout efficiency
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Neighbour triggers: example of application
• Drift of charge carriers induces a signal on adjacent electrodes
• The horizontal position can be calculated as a function of the induced
charges
• The amplitude of the signal in the adjacent strips can be lower than
the trigger threshold  need neighbour triggers
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DPP for the Charge Integration
(DPP_CI)
• Digital implementation of the QDC + discriminator and gate generator
• Implemented in the 12 bit, high speed digitizers ( Mod. 720(*) )
• Self-gating integration; no delay line to fit the pulse within the gate
• Automatic pedestal subtraction
• Extremely high dynamic range
• Dead-timeless acquisition (no conversion time)
• Energy and timing information can be combined
• Typically used for PMT or SiPM/MPPC readout and for gamma-neutron
discrimination in scintillating detectors
(*) Implementation in the Mod751 is being studied
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DPP-CI Block Diagram
IN P U T
b = R is e T im e
T h r = T R G T h re s h o ld
Q L S B = T S * V L S B / 50
= 40 fC (M od 720 )
T IM IN G
F IL T E R
a = Low Pass m ean
W = G a te w id th
G ATE
N s b l = B a s e lin e m e a n
C LK
T IM E S T A M P
COUNTER
a b
D ELAYED
IN P U T
Thr
T R IG G E R
D = D e la y (P re -G a te )
COMP
T R G & T IM IN G
F ILT E R
W
GATE
M O N O S T A B LE
IN P U T
D
D E LA Y
Nsbl
B A S E LIN E
M EAN
SUB
A C C U M U LA T O R
(IN T E G R A T O R )
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CHARGE
DPP-CI / Analog Chain set-ups
N1470
High
Voltage
Delay
N108A
QDC
V792N
Charge
TDC
V1190
Time
Splitter
A315
CFD
N842
Dual Timer
N93B
PMT
NaI(Tl)
DT5720
12bit @ 250MSps
Digitizer + DPP-CI
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Charge
Time
DPP-CI vs Analog Chain
• PROs
–
–
–
–
–
–
–
–
–
–
All in one board
Stability and reproducibility Flexibility
(FPGA based algorithms)
Self-Independent-Retroactive-Adaptive Gate
No conversion time (dead-timeless acquisition)
Baseline restoration
Accept positive, negative and bipolar signals
Extremely wide Dynamic Range
Coincidences between couples of channels
Total Cost per Channel
• CONs
– Parameters set-up (need good software interface)
– Getting started more difficult
– Channel density
Energy Resolution? Better or worse depending on the conditions
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DPP-CI: Test Results
NaI detector and PMT directly
connected to the QDC or digitizer
Resolution = FWHM * 100 / Mean
DPP-CI
Analog QDC
Energy (MeV)
Res (%)
Res (%)
0.481 (137Cs Compton edge)
9.41  1.18
12.80  0.70
0.662 (137Cs Photopeak)
7.01  0.04
8.17  0.04
1.33 (60Co Photopeak)
5.67  0.03
6.66  0.18
1.17 (60Co Photopeak)
5.46  0.02
5.89 0.13
2.51 (60Co Sum peak)
3.82  0.11
4.10  0.24
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DPP-CI: Other Tests
• Tested with SiPM/MPPC detectors at Univerità dell’Insubria (Como –
Italy) and in CAEN (2009/2010):
Dark Counting Rate
LED pulser
Readout of a 3x3mm Lyso Crystal + Gamma source
Readout of a scintillator tile for beta particles
•Threshold scan
–
–
–
–
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•0.5 ph
•1.5 ph
•2.5 ph
DPP for -n Discrimination
• Digital implementation of the E/E or Rise Time discriminator (both are
Pulse Shape Analysis)
• Digital E/E: double gate charge integration (same as DPP-CI but with
two gates); applied to fast output (typ. organic liquid scintillators)
• Digital Rise Time discrimination: T in the Zero Crossing of two CFDs at
25% and 75%; applied to integrated output (either from C.S. preamp or
digital integrator)
• PSA used to discard unwanted events (typ. gammas); good events
saved including waveform, energy and time stamp
• Dead-timeless acquisition (no conversion time)
• Algorithms tested at Duke University on July 2010 (off-line). FPGA
implementation in progress.
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-n Discrimination Block Diagram (I)
Algorithms tested off-line
Firmware being implemented
SHORT GATE
LO N G G A T E
T R G th r
COMP
T IM E
COUNTER
T R IG G E R
T IM E S T A M P
W AVEFORM
Q -F A S T
IN P U T
SUB
D E LA Y
A C C U M U LA T O R
(IN T E G R A T O R )
Q -S L O W
B A S E LIN E
P re T rig g e r
BLns
B L th r
GATE1
GATE2
G a te W id th 1 G a te W id th 2
P U LS E S H A P E
D IS C R IM IN A T O R
P S D th r
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E V E N T B U IL D E R
C LK
OUT
DATA
-n Discrimination Block Diagram (II)
Algorithms tested off-line
Firmware not planned
T
C LK
T IM E S T A M P
T IM E
COUNTER
T R G th r
COMP
IN P U T
SUB
D ELAY
B A S E L IN E
PU LSE SH APE
D IS C R IM IN A T O R
CFD
D ELAY
25% ATTEN
SUB
ZC
75% ATTEN
SUB
ZC
T1
P re T rig g e r
BLns
B L th r
T2
P S D th r
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E V E N T B U IL D E R
W AVEFORM
OUT
DATA
-n Discrimination: preliminary results (I)
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-n Discrimination: preliminary results (II)
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-n Discrimination: preliminary results (III)
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-n Discrimination: preliminary results (IV)
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DPP for Time Measurements
• Digital implementation of the TDC + CFD
• DPP-TF and DPP-CI give time stamps with the resolution of the sampling
period (10 ns and 4 ns,  = Ts/12); no interpolation for better timing
information
• Digital algorithms to implement Constant Fraction Discriminators or
Timing Filters (RC-CRN)
• Extremely high dynamic range
• Dead-timeless acquisition (no conversion time); can manage long bursts
of pulses (theoretical unlimited double pulse resolution)
• Interpolation between a set of samples can increase the resolution well
beyond the sampling period (up to picoseconds)
• Big dependence of the resolution from the rise-time and
amplitude of the pulses (V/ T)
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Digital algorithms for Timing Analysis
• Positive/negative pulses digitally transformed into bipolar pulses
• The Zero Crossing doesn’t depend on the pulse amplitude
• Timing filters: RCN or Digital CFD
• Optional RC filter (mean filter) to reduce the HF noise
• ZC interpolations:
• Linear (2 points)
• Cubic (4 points)
• Best fit line or curve (4 or more points)
H igh R esolution Z C after
m ath. Interpolation
S1
S2
T im e
IN P U T
S3
S 4 = Z C tim e stam p
R esolution = T s / 12
S4
T im in g
F ilte r
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Digital CFD and Timing Filters
e
-t/T
IN P U T
-(1 /T )
1
st
e
-t/T
C R F ilte r:
d e riv a tiv e
2
(1 /T )
e
-t/T
2
C R F ilte r:
nd
2 d e riv a tiv e
K
e
-t/T
D = C F D d e la y
K =
f (D , F )
F = C F D F ra c tio n
D ig ita l
CFD
NOTE: the higher ZC slope and the lower tail, the better filter
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ZC timing errors
•
T SAMPL
The timing resolution is affected by three main
sources of noise:
–
ANALO G
S IG N A L
–
–
S N+1
Ei
•
Both simulations and experimental test
demonstrate that there are two different regions:
•
When Rise Time > 5*Ts the pulse edge can be
well approximated to a straight line, hence Ei is
negligible. The resolution is proportional to the
rise time and to the number of bits of the ADC.
•
When Rise Time < 5*Ts the approximation to a
straight line is too rough and Ei is the dominant
source of error. The resolution is still proportional
to the number of bit but becomes inversely
proportional to the rise time. Resolution
improvement expected for cubic interpolation.
•
The best resolution is for Rise Time = 5*Ts,
regardless the type of digitizer
•
The resolution is always proportional to the pulse
amplitude (more precisely to the slope V/T)
ze ro
Eq
L IN E A R
IN T E R P O L A T IO N
LS B ADC
SN
Electronic noise in the analog signal (not
considered here)
Quantization error Eq
Interpolation error Ei
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Sampling Clock phase effect (RT<5Ts)
(I)
When rise time < 5*Ts, the interpolation error has a big variation with the phase
between the rising edge and the sampling clock.
D E L A Y A -B = N *T S
CHA
ERRA
D E L A Y A -B = (N + 0 .5 )*T S
ERRA
TIMEAB
CHB
DELAYAB = N * Ts:
same clock phase for A and B 
same interpolation error 
ERRA  ERRB 
Error cancellation in calculating TIMEAB
ERRB
CHA
CHB
ERRB
DELAYAB = (N+0.5) * Ts:
rotated clock phase for A and B 
different interpolation error 
ERRA  ERRB 
No error cancellation. ERRA and ERRB
are symmetric: twin peak distribution
= (ZCA + ERRA) – (ZCB + ERRB) = ZCA– ZCB + (ERRA - ERRB )
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Sampling Clock phase effect (RT<5Ts)
9
0
0
8
0
0
7
0
0
'
h
i
s
t
o
_
M
o
d
7
2
4
_
d
t
1
0
n
.
t
x
t
'
'
h
i
s
t
o
_
M
o
d
7
2
4
_
d
t
1
5
n
.
t
x
t
'
DELAY = N * Ts
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
DELAY = (N + 0.5) * Ts
0
0
2
0
0
4
0
0
6
0
0
8
0
0
1
0
0
0
1
2
0
0
1
4
0
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0
1
6
0
0
(II)
Sampling Clock phase effect (RT<5Ts)
10
Vpp = 100mV
Mod1751: 10bit 1GSps
Rise Time = Ts
Mod1720: 12bit 250MSps
14bit – 100MSps
Mod1724: 14bit 100MSps
Emulation
12bit – 250MSps
1
Std _ D e v [n s ]
10bit – 1GSps
0.1
0.01
0.5
1
1.5
2
Delay in Ts
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2.5
(III)
Sampling Clock phase effect (RT<5Ts)
10
RiseTime 5ns
Vpp = 100mV
5 ns
10 ns
RiseTime 15ns
Rise Time 15 ns
RiseTime 20ns
20 ns
RiseTime 30ns
30 ns
RiseTime 10ns
Mod720: 12bit 250MSps
Emulation
Std _ D e v [n s ]
1
0.1
0.01
3
4
5
6
7
8
Delay[ns]
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9
(IV)
Preliminary results: Mod724
(14 bit, 100 MS/s)
StdDev (ns)
DELAYAB = (N+0.5) * Ts (worst case)
RiseTime (ns)
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Preliminary results: Mod720
(12 bit, 250 MS/s)
StdDev (ns)
DELAYAB = (N+0.5) * Ts (worst case)
RiseTime (ns)
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Preliminary results: Mod751
(10 bit, 1 GS/s)
StdDev (ns)
DELAYAB = (N+0.5) * Ts (worst case)
NOTE: the region with Rise Time < 5*Ts (5 ns) is missing in this plot
RiseTime (ns)
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Mod724 vs Mod720 vs Mod751
StdDev (ns)
Amplitude = 100 mV
RiseTime (ns)
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Mod751 @ 2 GS/s
StdDev (ns)
The cubic interpolation can reduce the gap between best and
worst case as well as increase the resolution for small signals!
  2 ps !
Amplitude (mV)
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DPP for Pulse Counting (SCA)
• Digital implementation of the discriminator + scaler (Single-Channel
Analyzer)
• Can be implemented in the high density digitizers (mod. 740)
• Pulse Triggering: baseline restoration, noise rejection, etc…
• Single or Multi-Channel Energy Windowing
T h rH
T h rL
T h rH
COMP
IN P U T
C R -R C
COUNTER
A C T IV IT Y
T h rL
COMP
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DPP readout modes
Waveform mode
•
same operating mode of the standard firmware (except for the individual pulse
triggering). 1 event = record of samples (waveform). Typ. thousands of numbers.
•
The memory buffer contains one acquisition window (1 trigger  1 buffer)
•
Mainly used for debugging and parameters setting
•
High data throughput  low counting rate (typ. < 1KHz)
•
The waveform mode allows the users to develop and test new DPP algorithms (off-line
analysis)
List mode
•
1 event = 1 or 2 numbers: Energy (Charge or Height) and/or Time Stamp
•
The memory buffer contains many events (N triggers  1 buffer)
•
Small event size  high counting rate (1 MHz or more)
•
Histograms, coincidences, etc… easily implemented off line
Mixed Mode
•
Energy and/or Time stamps saved together with a small piece of waveform for postanalysis.
•
1 event = ~100 numbers. 1 buffer = N events.
•
On-line pulse shape discrimination for event validation (discard unwanted events)
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Building new DPP algorithms
• The digitizer is a general purpose acquisition module; in most cases it
requires a dedicated firmware or software to implement a specific
application
• The first algorithm validation can be done using software signal
emulators (mathlab, LabView, C/C++, etc…). Everything happens
inside the computer
• Then it is then possible to verify the algorithms applying them to real
data read from the digitizer in oscilloscope mode (DPP off-line)
• Once validated, the algorithm must be implemented in the FPGA
(VHDL or Verilog) of the digitizer
• Finally, the algorithm can be tested on-line
• CAEN is open to collaborate with the customers at any level of the
previous design flow
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CAEN Waveform Digitizers
•
•
•
•
•
•
•
•
• From 2 to 64 channels
• Up to 5 GS/s sampling rate - Up to 14 bit
• FPGA firmware for Digital Pulse Processing
VME, NIM, PCI Express and Desktop
VME64X, Optical Link (CONET), USB 2.0, PCI
Express Interfaces available
Memory buffer: up to 10MB/ch (max. 1024 events)
Multi-board synchronization and trigger
distribution
Programmable PLL for clock synthesis
Programmable digital I/Os
Analog output with majority or linear sum
FPGA firmware for Digital Pulse Processing
–
–
–
–
–
–
–
–
•
Zero Suppression
Pulse Triggering
Trapezoidal Filters for energy calculation
Digital CFD for timing information
Digital Charge Integration
Pulse Shape Analysis
Coincidence
Possibility of customization
Software Tools for Windows and Linux
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Digitizers Table
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Mod724: 14 bit, 100 MS/s
•
Very high resolution and low noise digitizer
•
DPP-TF for Pulse Height Analysis (Trapezoidal Filters)
•
Replacement of the shaping amplifier + peak sensing ADC
•
Three dynamic range options (500mVpp, 2.25Vpp and 10Vpp)
•
Best suited for very accurate energy measurements
•
Good timing resolution with slow signals (rise time >= 50 ns)
•
Mid-Low speed signals (Typ: output of charge sensitive preamplifiers)
•
Applications:
• Spectroscopy (MCA) with Ge, Si and other detectors
• Any application using charge sensitive pre-amplifiers
• Low noise applications
• Neutrino and dark matter physics
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Mod720: 12 bit, 250 MS/s
•
Best compromise between resolution and speed
•
DPP-CI for Charge Integration
•
Best suited for PMT and SiPM/MPPC readout
•
Mid-High speed signals (Typ: output of PMT/SiPM)
•
Good timing resolution with fast signals (rise time < 100 ns)
•
Applications:
• Spectroscopy with NaI, CsI and other detectors (fast pre-ampli)
• Gamma Neutron discrimination
• Single Photon Counting
• PET
• Homeland Security
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Mod740: 12 bit, 65 MS/s
•
High channel density
•
No DPP available (few FPGA resources)
•
Best suited for high density systems
•
Low speed signals (Typ: output of sensors, CCDs or shaping amplifiers)
•
Applications:
• Sensors readout (temperature, pressure, CCD, etc…)
• Coincidence Matrix
• Imaging
• Single channel analyser
• Readout of Shaping Amplifiers
• TPC readout systems
• Any application with many channels
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Mod751/761: 10 bit, 1-2-4 GS/s
•
Very high sampling rate
•
2 GS/s: half channels; 4GS/s: one fourth channels
•
No DPP available (DPP-CI perhaps available in the future)
•
Best suited for very high speed detectors (diamond? LaBr? …)
•
High speed signals (Typ: output of wideband amplifiers)
•
Applications:
• Diamond detectors
• RPC readout systems
• Time of flight
• Fast PMT readout
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Mod721/731: 8bit, 0.5-1 GS/s
•
Precursor of the Mod751; today its low cost version
•
No DPP available
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Mod742: 12bit, 5 GS/s
•
Excellent combination of very high sampling rate, resolution and high density
•
Based on the DRS chip (developed by S. Ritt at PSI)
•
No DPP available (at least for the moment)
•
Best suited for very high energy and timing resolution applications
•
Very high speed / high dynamics signals
•
Mixed fast and slow acquisition mode
•
50-100us Dead Time: not suitable for high counting rate
•
Max. 1024 points: not suitable for long pulses
•
Applications:
• Fast detector test benches
• Cherenkov Telescopes
• Ultra precise Pulse Shape discrimination
• Very high resolution TDC (5-10 ps)?
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DPP firmware table
Name
Mod
Status
Detectors (typ.)
Notes
DPP-TF
724
Ready
Hi res. Si, Ge
Pulse Height analysis (Trapezoidal Filters)
DPP-CI
720
Ready
PMT, SiPM
Charge Integration (digital QDC)
DPP-NG
720
Q1 2011
Organic liquid
-n Discrimination
DPP-SG
724
Q1 2011
Segmented/Strip
DPP-TF for Segmented detectors
DPP-FCI
751
t.b.d.
diamond
Charge Integration with fast signals
DPP-PC
740
t.b.d.
Plastic, strips
Pulse Counting
DPP-TDC
751
761
742
t.b.d.
High Res Timing
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Experimental Demo 1
N1470
High
Voltage
60Co
USB
850V
NaI(Tl)
PMT
Charge Sensitive
Preamplifier for PMT
DT5724
Energy
14bit @ 100MS/s
Digitizer + DPP-TF
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Experimental Demo 2
N1470
High
Voltage
60Co
USB
-650V
DT5720
LaBr3
PMT
Charge
12bit @ 250MS/s
Digitizer + DPP-CI
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Experimental Demo 3
Trigger
USB
H IG H V O L T A G E
B IA S G E N E R A T O R
2 G H z , 0 -5 0 d B
V A R IA B L E G A IN
W ID E B A N D A M P L IF E R
LED
PULSER
DT5720
Charge
12bit @ 250MS/s
Digitizer + DPP-CI
S iP M
SP5600
USB
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Experimental Demo 4
N1470
High
Voltage
USB
210Po
450V
1.6 GHz – 52dB
WideBand Amplifier
DT5751
Waveform
10bit @ 2GS/s
Digitizer
DPP off-line
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