Transcript 5 4장. HW/SW Co-Design for SoC

Network on Chip
4장. HW/SW Co-Design for SoC
Levels of IC architecture
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4장. HW/SW Co-Design for SoC
Emerging Platforms &
Architectures
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4장. HW/SW Co-Design for SoC
NoC (network on chip)
U.C. Berkeley
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단일 반도체 칩 상에 통신망 구조를 이식
OSI model에 의해서 전송 프로토콜을 정의
DSP/microprocessor/Memory 등을 H/W-S/W co-design 이용 단일 칩 내
에서 연결
코드 최적화 및 저전력 software IP 라이브러리 구축
모듈간 연결을 위한 버스 구조
구성 요소
 Region: 특수한 토폴로지/네트워크 구조를 허용하는 영역
 Backbone
 Wapper : 전송되는 메시지를 적절한 형태로 변환, 복잡하다
복잡하고 대형 시스템에 적합
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4장. HW/SW Co-Design for SoC
Wires-Centric Design
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Exploits logic structure to reduce wire loads
Enables use of advanced circuits
 wire properties and crosstalk known early and well
characterized
Gives a stable design
 key wire loads don’t change with small logic
changes
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4장. HW/SW Co-Design for SoC
Wires dominate - power, area, delay
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Problem - Contemporary tools leave wires as an
afterthought
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Solution 1 - wires first design
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result is lack of structure, visibility, and control
route key wires, then place gates
Solution 2 - route packets, not wires
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on-chip networks
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global wires fixed before the design starts
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4장. HW/SW Co-Design for SoC
Wires-first design
Short
Wire
Models
Structured
RTL
RTL
Floorplan
Structure
Synthesis
Local
Netlists
Place &
Route
Layout
Regions
Key Wires
Placement
& Loads
Wire plan
Manual
Design
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Library
Slow
Paths
Timing
Analysis
R&C
Extractor
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4장. HW/SW Co-Design for SoC
On-Chip Interconnection
Networks
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Replace dedicated global wiring with a shared network
Local
Logic
Router
Network
Wires
Dedicated wiring
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Chip
Network
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4장. HW/SW Co-Design for SoC
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4장. HW/SW Co-Design for SoC
Bus-versus-Network
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4장. HW/SW Co-Design for SoC
NoC Challenges:
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4장. HW/SW Co-Design for SoC
Physical Issues
Challenges
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4장. HW/SW Co-Design for SoC
Most Wires are Idle Most of
the Time
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Don’t dedicate wires to signals, share wires across multiple
signals
Route packets not wires
Organize global wiring as an on-chip interconnection network
allows the wiring resource to be shared keeping wires busy most of
the time
 allows a single global interconnect to be re-used on multiple
designs
 makes global wiring regular and highly optimized
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4장. HW/SW Co-Design for SoC
Dedicated wires vs. Network
D e d ica te d W irin g
O n -C h ip N e tw o rk
S p a g h e tti w irin g
O rd e re d w irin g
V a ria tio n m a ke s it h a rd to m o d e l
cro ssta lk, re tu rn s, le n g th , R & C .
N o va ria tio n , so ea sy to ex a ctly
m o d e l X T , re tu rn s, R a n d C .
D rive rs size d fo r ‘w ire m o d e l’ –
9 9 % to o la rg e , 1% to o sm a ll
D rive r size d e xa ctly fo r w ire
H a rd to u se a d va n ce d sig n a lin g
E a sy to u se a d va n ce d sig n a lin g
Lo w d u ty fa cto r
H ig h d u ty fa cto r
N o p ro to co l o ve rh e a d
S m a ll p ro to co l o ve rh e a d
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4장. HW/SW Co-Design for SoC
Ideas from Networking and VLSI
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4장. HW/SW Co-Design for SoC
Structural layers of NOC
Product
Configuration
Network management, allocation, operation modes
Applications
Resource management, diagnostics, applications
Functions
Executables
Hardware units
Resources
Regions
Communication
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System control, product behaviour
Execution control, functions
RTOS, code, HW configurations
Processors, memorires, configurable HW, logic
Resource types, buses, IO
Region types, switches, network interfaces
Channels and protocols
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4장. HW/SW Co-Design for SoC
Network protocol
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Application
System/Session
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Transport
Network
Data link
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Physical
 신호 전압, 타이밍, 버스 폭, 신호 동기
Data link
 오류 검출 정정
 Arbitration of physical medium
Network
 IP protocol
 데이터 라우트
Transport
 TCP 프로토콜
 End –to-end connection
Physical
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4장. HW/SW Co-Design for SoC
NOC Platform development
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Scaling problem
 How big NOC is needed? What are the application area requirements?
Region definition problem
 What kind of regions are needed? What kind of interfaces between regi
ons? What are the capacity requirements for the regions?
Resource design problem
 What is needed inside resources? Internal computation type and intern
al communication?
Application mapping flow problem
 What kind of languages, models and tools must be supported? How to
validate and test the final products?
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4장. HW/SW Co-Design for SoC
NOC Application Development
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Mapping problem
 How to partition applications for NOC resources? How to allocate functional
ity effectively? Is the performance adequate? Is the resource usage in balan
ce?
Optimisation problem
 How to perform global optimisation of heterogenuous applications? How to
define right optimisation targets? How to utilise application/resource type s
pecific tools?
Validation problem
 Are the contraints met? Are the communication bottlenecks or power consu
mption hot spots? How to simulate 10000 GIPS system? How to test all appl
ications?
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4장. HW/SW Co-Design for SoC
NoC-Based System Design -I
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4장. HW/SW Co-Design for SoC
NoC Based System Design -II
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4장. HW/SW Co-Design for SoC
NoC-Based System Design III
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4장. HW/SW Co-Design for SoC
Summary of NoC Systems Design
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4장. HW/SW Co-Design for SoC
스위치 네트워크: CLICHE
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OSI 모델을 데이터 전송 프로토콜로 사용
칩에 집적된 네트워크 (Network on Chip)
패킷 데이터 전송
대형 시스템이 구성 요소
이종 구성 요소의 칩 레벨 집적에 유리하다.
switch
SWITCH
S
rni
rni
P
mux
rni
resource
M
resource
queue
c
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rni
rni
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rni
queue
rni
P
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rni
resource
resource
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re
rni
resource
S
rni
resource
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P
c
rni
Selection
logic
mux
c
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mux
P
S
rni
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re
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Selection
logic
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Selection
logic
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resource
M
rni
resource
Selection
logic
rni
resource
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rni
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lo ctio
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mux
rni
resource
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queue
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4장. HW/SW Co-Design for SoC
Square Switch
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4장. HW/SW Co-Design for SoC
Regions
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4장. HW/SW Co-Design for SoC
Physical Layer
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4장. HW/SW Co-Design for SoC
Physical Layer
Phenomenon
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4장. HW/SW Co-Design for SoC
Data Link Layer
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4장. HW/SW Co-Design for SoC
Advanced Bus
Techniques*
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4장. HW/SW Co-Design for SoC
Network Layer
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4장. HW/SW Co-Design for SoC
SPIN NoC*
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4장. HW/SW Co-Design for SoC
Transport Layer
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4장. HW/SW Co-Design for SoC
Application Program Layer
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4장. HW/SW Co-Design for SoC
Application (Software) Layers
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4장. HW/SW Co-Design for SoC
NoC Operating System
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4장. HW/SW Co-Design for SoC
NoC 의 figure of Merit
Computation
Storage
Communication
Scalability
Efficiency
Energy Utilisation
Fault tolerance
Result quality (accuracy)
Responsiveness
consumption
Capacity
Functionality
Performance
Structural
Functional
Control
Complexity
System
Quality
Cost
Variability
Materials
Licencing
Production
Implementation
Development
Flexibility
Applicability
Configurability
Programmability
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Modifiability
Coupling
Cohesion
Modularity
Volume
Lifetime
Usability
Manufacturability
Effort
Time
Risk
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4장. HW/SW Co-Design for SoC
NoC 설계 flow
R. Marculescu
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4장. HW/SW Co-Design for SoC
NoC기반의 응용 분야
Low Power communication systems
High-perforrmance
communication systems
Baseband platform
High-capacity
communication systems
Database platform
Personal
assistant
Data
collection
systems
BACKBONE
Entertainment
devices
Multimedia platform
PLATFORMS
SYSTEMS
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Virtual reality games
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4장. HW/SW Co-Design for SoC
Layered Radio Architecture
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4장. HW/SW Co-Design for SoC
Stream-based design
Stream Packet
Processing
Element 1
Stream Packet
Processing
Element 2
Configuration
Pipeline
Application Layer Software
I/O Layer
Configuration Layer
Processing Layer
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Stream Packet
Interpret
Packet
Processing
Pipeline
Bypass
Pipeline
ReConstr.
Packet
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4장. HW/SW Co-Design for SoC
NoC의 저전력 문제
어플리케이션 레이어
- DPM, 리소스 관리, 전력 관리 API
트랜스포트 레이어
- QoS 보장 (지연 및 메시지 손실 최소)을 위한 데이터
패킷 관리 문제, 메시지를 통한 PSM
네트워크 레이어
packetized 데이터 전송시 스위칭 및 라우팅 문제
데이터 링크 레이어
패킷 데이터 에러 손실 감축 및 복구 문제
Physical 레이어
- DVS에 따른 신뢰성 문제, 온 칩 동기 문제
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4장. HW/SW Co-Design for SoC
Tile-based Architecture Platform
R. Marculescu
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4장. HW/SW Co-Design for SoC
Energy-Aware Mapping for Tilebased Architectures
R. Marculescu
Objective: minimize the total communication
energy consumption
Constraint: meet the communication performance
constraints (specified by designer)
For a 4X4 tile architecture, 16! mappings
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4장. HW/SW Co-Design for SoC
OFDM + CDMA2000 통합 Baseband 프로세서에 적용
CDMA2000
RF
Conversion
to IF
and A/D
Modulator
Demodulator
Despreader
Searcher
Time Tracker
AFC
Channel estimator
Lock detector
RAKE combiner
Power control
Channel codec
Rate matching
Multiplexing
HW/SW Co-design
CDMA2000
S/W part(DSP)
OFDM
S/W part(DSP)
H/W part
(ASIC)
Interconnection
(NoC)
OFDM
I/Q Demodulator
FFT Mode
Guard Interval
Symbol TimingRecovery
Carrier Recovery
Channel Estimator
Equalizer,
FEC
Noise Filter
FFT
Baseband processing
I/O controller
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Process controller
Program memory
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4장. HW/SW Co-Design for SoC
NoC Examples
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[Adriahantenaina et al., 2003] Adriahantenaina, A., Charlery, H., Greiner, A., Mortiez, L.,
and Zeferino, C. A. (2003). SPIN: a scalable packet switched on-chip micronetwork. In
Proceedings of the Design Automation and Test Conference - Designer's Forum, pages
70{79.
[Alho and Nurmi, 2003] Alho, M. and Nurmi, J. (2003). Implementation of interface
router IP for Proteo network-on-chip. In Proc. The 6th IEEE International Workshop
on Design and Diagnostics of Electronics Circuits and Systems (DDECS'03), Poznan,
Poland.
[Goossens et al., 2003] Goossens, K., Dielissen, J., van Meerbergen, J., Poplavko, P.,
Radulescu, A., Rijpkema, E., Waterlander, E., , and Wielage, P. (2003). Guaranteeing
the quality of services in networks on chip. In Jantsch, A. and Tenhunen, H., editors,
Networks on Chip, chapter 4, pages 61{82. Kluwer Academic Publishers.
[Karim et al., 2001] Karim, F., Nguyen, A., Dey, S., and Rao, R. (2001). On-chip
communication architecture for OC-768 network processors. In Proceedings of the
Design Automation Conference, pages 678{683.
[Nilsson et al., 2003] Nilsson, E., Millberg, M., •Oberg, J., and Jantsch, A. (2003).
Load distribution with the proximity congestion awareness in a network on chip. In
Proceedings of the Design Automation and Test Europe (DATE), pages 1126{1127.
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Some more technologies
John Stockton
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Ad-hoc wireless networking, networks of sensors
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Emerging Zigbee wireless standard
UC Berkeley’s Smart Dust Project
Dust-Inc. (UC Berkeley spin-off company)
IEEE 802.15.4 Radios
• Hybrid CMOS SOM (System on Module) Solutions:
– MEMS structures fabricated on top of CMOS
– Film Bulk Acoustic Resonators (FBARs) over CMOS
– Chemical sensors over CMOS
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4장. HW/SW Co-Design for SoC
John Stockton’s view
StockLabs Venture Consulting
• Software & Compilers will drive chip architecture
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Processor architecture matters less and less
Custom datapaths by compilers replace specialized instrs
10’s of processors per chip, MIMD becomes a way of life
“Freedom from Choice” - enables SOC scalability
• Chip Industry evolves to three levels of granularity
– FPGAs as we know them today, flexible but low performance
– Coarse-Grained FPGAs, better perf, but lose some flexibility
– Structured ASIC with embedded reprogramability
• Software industry finally “gets it” on reliability / quality
– Gains some of the discipline (restrictions) of the IC industry
– Trades CPU Cycles for more robust applications
www.stocklabs.com
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4장. HW/SW Co-Design for SoC
Some Companies to watch
John Stockton
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4장. HW/SW Co-Design for SoC
참고문헌
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The Codesign of Embedded Systems : A Unified
Hardware/Software Representation, Sanjaya Kumar, James
H.Aylor, Barry W.Johnson, Wm. A. Wulf
Synthesis and simulation of digital systems containing interacting
hardware and software components 29th dac
A model and methodology for hardware-software codesign
CAP Laboratory Homepage (http://peace.snu.ac.kr/)
Pai Chou, Ross Ortega, Gaetano Borriello, "Synthesis of the
Hardware/Software Interface in Microcontroller-Based Systems,"
Proceedings of the IEEE/ACM International Conference on
Computer-Aided Design, Santa Clara, CA, November 1992.
pp.488-495.
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