Transcript HW/SW Co-simulation Platform - ESA Microelectronics Section

HW/SW SystemC
Co-Simulation SoC Validation
Platform
Thomas Schuster
Outline
1.Introduction
TU Braunschweig/IDA
2.Study Objectives & Organization
3.Virtual Platform Infrastructure
4.Development of TLM 2.0 Simulation Models
5.Proof-of-concept VP
1. TECHNISCHE UNIVERSITÄT
BRAUNSCHWEIG
14.000
3.000
1.600
5
40
Students
University staff
Scientists
Departments
Degree Programs
Founded in 1745
(oldest university of
technology in Germany)
School of
Carl-Friedrich Gauß
IDA Institute of Computer and
Communication Network Engineering
Institute of Computer and Communication Network Engineering
director: Prof. Rolf Ernst
computer aided
embedded
system design
embedded
computers
for space
applications
communication
networks
Prof. Admela
Jukan
VLSI systems
design
Prof. Mladen
Berekovic
Prof. Rolf
Ernst
Prof. Harald
Michalik
cryptography
sponsored by
Intel
Prof. Wael Adi
• ca. 60 employees (21 univ. funded)
• ca. 2.2 Mio. € 3rd party funding in 2006
• part of department of EE&IT
staff
secretariat
accounting
system
administration
electronic
lab
mechanical
lab
People involved
IDA:
Prof. Dr. Harald Michalik
Prof. Dr. Mladen Berekovic
Study Management
Chief Technical Scientist
Thomas Schuster
Dennis Bode
Bjoern Osterloh
Study Engineer
Study Engineer
Study Engineer
ESA Supervisors:
Dr. Luca Fossati
Dr. Laurent Hili
2. Project Objectives
• High-Level modeling of key IPs in TLM 2.0
• Functional validation and timing
accuracy analysis
• Power Modeling
• Definition of a design flow for VP modeling
• Selection of appropriate infrastructure
• Development of a proof-of-concept Virtual Platform
• Demonstration of a design space exploration
www.vlsilab.org
Study Organization
Jan 2010
today
July 2011
Virtual Platform / Advantages
A Virtual Platform is an abstract hardware model that is
simulated by software.
VPs can easily be duplicated
and packaged allowing
multiple developers
to work in parallel.
Unlike physical hardware
VPs provide observability
and controllability for the entire
system.
Software development can start
before hardware prototypes are
available.
Productivity
Availability
Accessibility
Consistency
VPs can be cosimulated/emulated. Gradual
refinement from high abstraction
to RTL eases verification.
3. Selection of VP Infrastructure
Requirements:
• Open Source (GPL, L-GPL)
• Support for TLM 2.0 (LT and AT)
• Concept for development of:
- memory mapped devices
- complex bus models
• Vendor tool independence
System shall be developed around TRAP
(Transaction level Automatic Processor generator)
http://code.google.com/p/trap-gen/
Survey on Tools & Techniques
VPI
Originated by
License
Pros
Cons
Coware Virtual
Platform
Coware Inc.
Com
+ runtime
Sophisticated,
Processor Designer,
in-house expertise
expensive
Carbon SoC Designer
Carbon Design Systems
Com
+ runtime
Sophisticated,
Model Compiler
expensive
OVP
Imperas
semi-com
TLM 2.0 compliant,
large open component lib,
widespread
simulator not
open-source
SOCLIB
ANR project
(ST, Thales, …)
GPL
Widespread, large
community
no TLM 2.0
UNISIM
HiPEAC project
INRIA
BSD
Existing component library
no TLM 2.0
contrib. slow down
ReSP
ESA project
Politecnico di Milano
GPL
Existing components
(LEON), ESA affiliation
no TLM 2.0
contrib. low
GreenSocs
GreenSocs Ltd.
GPL
TLM 2.0, TU-BS expertise
-
Open Tools for TLM 2.0 are hard to find.
is closest to requirements
Mission:
• Provision of vendor-independent infrastructure
• Open platform for joint IP development
Infrastructure (selected):
GreenBus
GreenReg
GreenControl
GreenScript
- Foundation for Bus Modeling with TLM 2.0
(incl. AMBA impl. almost ready-to-use)
- Framework for Register & Device Modeling
- Control and Configuration Interfaces (CCI)
- Methods and Tools for Use-Case capture
… and much more, see: www.greensocs.com
GreenSocs System Overview
Source: Mark Burton, GreenSocs
4. Modeling of SystemC IP
No.
IP
1
AMBA AHB
2
Aeroflex Gaisler GRLIB MCTRL Memory Controller
3
A memory model working with IP 2
4
A Harvard L1 cache
5
A SPARCv8 MMU or equivalent
6
Aeroflex Gaisler GPTIMER General Purpose Timer
7
Aeroflex Gaisler IRQMP Interrupt Controller
Models will be implemented in
LT and AT flavor of TLM 2.0
Transaction Level Modeling
Simulation Performance
Accuracy
Function calls through dedicated interfaces
model synchronization of
concurrent threads of execution.
TLM 2.0 Loosely Timed (LT) – blocking communication, temporal decoupling
TLM 2.0 Approximately Timed (AT)– non-blocking communication
2 Phase AT (begin request, end response)
4 Phase AT (begin/end request, begin/end response)
n Phase AT
Cycle Accurate SystemC or RTL simulation
Device Modeling with GreenReg
GreenReg
Protocol
(Socket)
Register Set
User Model
Regfile
callbacks
reg
reg
reg
behavior
timing
power
Example Slave Module
• Registers can be automatically hooked on sockets
• Registers provide Pre/Post Read/Write callbacks to behavior
Verification of IP Models
Reference Simulation (TLM/RTL)
Full TLM Simulation
test vectors
test vectors
TLM Stimuli/Monitor
AMBA
TLM/RTL Adapter
RTL
TLM Stimuli/Monitor
AMBA
TLM
Design Under Test
Design Under Test
Models will be evaluated with respect to
simulation performance & accuracy.
5. Proof-of-Concept VP
MEM
Aerofle
x
MCTRL
Status/Ct
rl Regs
MEM
Aeroflex
IRQMP
CAN
Space
Wire
Segmented
2x4
LEON
AHB
processors
SoC Wire
AMBA
Aeroflex
Aeroflex
GPTimer
Aeroflex
Aeroflex
GPTimer
GPTimer
GPTimer
MEM
Bridge
Bridge
Aeroflex
Aeroflex
GPTimer
Aeroflex
Aeroflex
GPTimer
GPTimer
GPTimer
Mem
AMBA
AMBA
LEON3
LEON3
LEON3
LEON3
LEON3
LEON3
LEON3
LEON3
Cache
Cache
Cache
Cache
Cache
Cache
Cache
Cache
MMU
MMU
MMU
MMU
MMU
MMU
MMU
MMU
Multi-Processor system stimulating all IPs generated in the course of the project.
Platform Software Architecture
Open Source Software Architecture:
Compiler
OS
GNU Compiler Collection
+
Embedded C library
Real-Time Executive for
Multi-processor Systems
A set of MiBench applications will be executed on top of RTEMS:
HW/SW SystemC
Co-Simulation Platform
Thank you for your attention!