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Designing a dual-fuel motor
management system with Zynq
Frank de Bont
Trainer / Consultant
BRINGING
YOU
BRINGING
YOU THE
THE NEXT
NEXT LEVEL
LEVEL IN
IN EMBEDDED
EMBEDDED DEVELOPMENT
DEVELOPMENT
_
_
Cereslaan 10b
5384 VT Heesch
+31 (0)412 660088
[email protected]
www.core-vision.nl
1
Agenda
Customer Requirements
Engine Management System
LNG Supply
Sensors / Actuators
AR Electronic Control Unit
Zynq Architecture
Design Flow and Tools
High-Speed ADC IP-block
Software Partitioning and Communication Channels
Why Linux with Xenomai
eMMC Configuration
Who is Core|Vision
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Customer Requirements
1
4
Design a dual-fuel motor management system
with real-time control
54255**slide
Hardware Platform Caterpillar 3500
Diesel
LNG (Liquefied Natural Gas)
High fuel efficiency
Start up on Diesel and then switch over to a mixture with LNG
Lowest possible emissions
NOx , SOx , CO2 and CH4 (methaan)
Easy to retrofit
Suitable for different qualities of LNG
Still 100% Diesel as a fall back
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Customer Requirements cont
1
4
Focus on motor management control also called
ArenaRed Electronic Control Unit
54255**slide
Hardware Platform Caterpillar 3500
Diesel
LNG (Liquefied Natural Gas)
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Engine Management System
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Engine Management System
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LNG Supply
Full controlled by the AR-ECU
A full fail-safe system
On-board diagnostics
Power and Temperature sensors
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Sensors / Actuators
Combustion in each cylinder is monitored by a set of
cylinder pressure sensors
These allows the AR-ECU to optimize the combustion timing
and gas mixture
In the exhaust are UEGO λ-sensors and temperature sensors
to monitor the results of each combustion cycle
Compressor
Filter
Intercooler
Boost
Wastegate
Inlet
Manifold
Turbo
Wastegate
Gas
P
P
P
P
T
Diesel
T
λ
Turbine
P
P
Pressure sensor
T
Temperature sensor
λ
Lambda (UEGO) sensor
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AR Electronic Control Unit
Connectors
Connectors
[PWR]
Power Supply Units
16
+5V
6
3
6
VR
Sensor
RS485
Interface
PHY
7
Termination
2 Kill / IRQ
22
Digital out
[AO]
Analog Out 4-20mA
4-20mA
driver
I/O Controller
I/O Controller
Diag
24V/5A
General Purpose
Out
+ Protection
2
UART
I/O Controller
Interrupt
Controller
4
4
Analog out
4
15
12
SWITCH
(3 ports)
4
3
1
Diag
24V/300mA
General
Purpose Out
+ Protection
I/O Controller
MII
2
4
RGMII
+24V
2
3
Digital out
[DO_LC]
Digital Output Low Current
4
Gbit Phy
8
COND
COND
Magnetics
Magnetics
8
8
Magnetics
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OBD/Debug
100Mb Link
Cascade
100Mb Link
Cascade
32
Digital in
8
ADC
42
ADC
4
RS485 TX
4
RS485 RX
3
VR
3
HALL sensor
12
Connectors
Shutdown
1
PWR
22
Preamp
Encoder
+8V
40 x
0-10V
and 2x
4-20mA
Gnd
+5V
+12V
Protection
Vbatt
UART
1
+24Vinj
Fire
Fault
8
2 Kill / IRQ
4
1
2
AR ECU x
I/O Controller
AR ECU x
2
CA Pulse
Synchroniser
4
42
_
8
8
8
8
UART
Fire
UART
Clock
I/O Controller
SPI Controller
32
10
[ETH]
Ethernet interfaces
[DI]
Digital Input
22Ch.
Ch.ADC
ADC
ADS8363
ADS8363
VRSensor
Sensor
VR
Interface
Interface
2
MCP3903
HALL
HALL
interrface
interrface
3
6 Ch. ADC
6MCP3903
Ch.
6 ADC
Remote
Shutdown
6x
RS422
RS422
PHY
PHY
3
CAT Data Link
+24V
1
10
[AI_HS]
Analog Input High
Speed
Rst
+24V
Fault
+24Vinj
3
2
[PWR]
Power Supply Units
+24Vinj
8
16
20
4
I/O Controller
SDIO
Controller
Memory
Controller
Configuration
JTAG
UART
Interrupt
Controller
Interrupt
Controller
I/O Controller
1
I/O Controller
2
[AI_LS]
Analog Input Low Speed
SPI
Controller
SPI
SPIController
Controller
CAN
Phy
MCP2551
[POS]
Position interfaces
I/O Controller
2
CAN
Controller
CAN
Ctrl
Zynq SoC
[SHD]
Remote
Shutdown
I/O Controller
2
MCP2551
2
[DO_HC]
Digital Output High Current
50 MHz
[EMD]
Electromechanical Drivers
I/O Controller
CAN
Phy
6
43
32
4
5
Diag
2
MCP2515
MCP2515
I/O Controller
CAN
14
I/O Controller
MCP2551
MCP2551
SPI
SPIController
Controller
12
CAN
CAN
Controller
Controller
CAN
Controller
CAN
CAN
CAN
Phy
Phy
[DL]
CAT data link
Internal
Expansion
Connectors
E-MMC
32GB
Data
6
8 x LED
SPI Flash
64Mb
2
1
1
DDR3
2x 2Gb
I/O Controller
JTAG
Connector
6
+12V
Watchdog and health
check uP
[CAN]
CAN interfaces
8 x EMD
ISOLATED
1
-15V
-15V
+15V
EMERGENCY
STOP
+5V
1
8 x EMD
ISOLATED
+8V
ESTOP
+12V
1
+15V
ESTOP OUT
Power Supply Units
for external supplies
+24V
+8V
Power Supply Units
for internal supplies
+24V
[STOP]
Emergency stop
Injector P
Injector N
D
D
ia
g
ia
g
16
9
AR Electronic Control Unit
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AR Electronic Control Unit cont
General Interfaces
DDR3 memory
eMMC
SPI Flash
JTAG
RS485
CAN
Ethernet
…
Monitor Interfaces
16x 12 bits ADC
2x UARTs
1x CAN
10x PWM outputs
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AR Electronic Control Unit cont
Electromechanical drivers
High Voltage IO
High Current IO
Digital Interfaces
High Current IO
Low Current IO
Sensor Inputs
Analog Interfaces
High Speed Inputs
Low Speed Inputs
Analog Outputs
Misc Interfaces
LED bank
Position Interface
Expansion Connector
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Catepillar 3500 & AR-ECU
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Zynq Architecture
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Zynq Architecture cont
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Zynq Architecture cont
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Zynq Architecture cont
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Zynq Architecture cont
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Design Flow and Tools
Software
Real-time OS
Drivers
APIs
...
Tools
Vivado SDK
Matlab
...
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FPGA hardware
ADC IP Interface
eMMC interface
DDR3 memory
IO
JTAG
...
Tools
Vivado
Matlab
ModelSim
Altium
...
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High-Speed ADC IP-block
High-Speed ADC to read
pressure sensors
AXI streaming interface for
transmitting ADC data
completed with timestamp and
crank angle
AXI slave interface for
configuration
Interface to 2 ADC channels
of the ADS8363
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High-Speed ADC IP-block cont
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High-Speed ADC IP-block cont
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Software Partitioning and
Communication Channels
Zynq SoC heart of the system
Linux with Realtime
extension Xenomai
Licensed & custom IP
in FPGA PL
Microprocessor for
Watchdog & Health
Monitor
Software controlled
EMD Injector Drivers
Communication
cascading channel
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Cascading Channels
Multiple AR-ECUs can be cascaded so the system can
control more than eight cyclinders.
AR-ECU
AR-ECU
#1
CA Pulse
Sync
Eth
100 Mb
Eth
1 Gb
Eth
100 Mb
AR-ECU
AR-ECU
#2
CA Pulse
Sync
Eth
100 Mb
Eth
1 Gb
Eth
100 Mb
AR-ECU
AR-ECU
#3
CA Pulse
Sync
Eth
100 Mb
Eth
1 Gb
Eth
100 Mb
Since Ethernet is non real-time by nature, crucial realtime signals will be routed over the four dedicated wires.
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Why Linux with Xenomai
Zynq All Programmable SoC dual core Cortex-A9
Xilinx offers a kernel build and Linux kernel distribution by 3rd
parties
Support Linux 3.14.17 with patches for real-time extension
Xenomai 2.6.4 within SDK, version choice is limited
Xenomai offers greater flexibility and consistency because the
real-time tasks can share the same drivers, synchronization
primitives and memory as other non real-time tasks
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eMMC Configuration
Initial Programming
Running
Bitfile Selection
Set boot mode pins of Zynq to
JTAG (can be forced in initial
programming U-boot)
Set boot mode pins of Zynq to
QSPI (can be forced in running
U-boot)
Start
Download initial programming
U-boot using JTAG
Download running U-boot using
QSPI
Updated
bitfile
present in
eMMC?
Start initial programming U-boot
Start running U-boot
Download initial programming
kernel, ramdisk image and DTB
files using TFTP
Download golden or updated
bitfile using eMMC
Start initial programming kernel
Download running kernel ramdisk
image and DTB files using eMMC
Run initial programming shell
scripts using rcS to download
from TFTP and program:
• Running U-boot + FSBL to QSP
• Running kernel to eMMC
• Running ramdisk to eMMC
• Running DTB to eMMC
• Golden bitfile to eMMC
• Update bitfile to eMMC
Program
FPGA
succesful?
Yes
No
Golden
image
present in
eMMC?
Yes
Program
FPGA
succesful?
Start running kernel
Yes
No
Stuck in U-boot, no valid FPGA
image found
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Yes
Done, FPGA loaded succesfully
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Flash Image Generation
Flash Image
Zynq
Configuration
Wizard
PS Register
Initialization
BootHeader
FSBL
(Executable)
Boot & Configuration
Information
PL
Bitstream(s)
FSBL
PL
Bitstream(s)
Flash Image
Generator
FSBL
(source Code)
User Created
OS and/or
Application
Code & data
OS and/or
Application
Code & data
Golden Image
(optional)
Golden Image
(optional)
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Core|Vision
Our competences
Core|Vision has more than 125 man years of design experience in hardand software development. Our competence areas are:
System Design
FPGA Design
Consultancy / Training
Digital Signal Processing
Embedded Real-time Software
App development, IOS Android
Data Acquisition, digital and analog
Modeling & Simulation
ASIC Conversion & Prototyping
PCB design & Layout
Doulos & Xilinx Training Partner
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?
?
Cereslaan 10b
5384 VT Heesch
+31 (0)412 660088
www.core-vision.nl
Email : [email protected]
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Visit our booth 28
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Training Program
Essentials of FPGA Design
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Training Program
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