Transcript Lecture9.1.ppt

Lecture 9.1
Building a FET
Integrated Circuits

CPU or Memory
– First Layer
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Transistors
Capacitors
Diode
Resistors
– Multi-layer
• Wiring
– Interconnects
– Bonding Pads
• Dielectric
• Capacitors
• Heterostructures
MOSFET in Memory Chip
Source
Gate
Drain
Field Effect Transistor (FET)
Voltage Controlled Resistor
Make Mask for Doping
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Clean wafer surface
Oxidize Si Surface
– How Thick is needed for Doping Mask?
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Spin on photoresist
Image photoresist
Develop photoresist
– Dissolve un-crosslinked photoresist
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Etch exposed SiO2 down to the Si of the wafer
Doping
Remove Implantation Mask
Silicon Oxidation
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Reactor
– Furnace at T=850C
– Pure Oxygen
• Si + O2  SiO2
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Kinetics
– BL-Mass Transfer
• J=Kg(CA-0)
– SS-Diffusion
• J=DO-SiO2 (dC/dx)
– Heat Transfer
• BL, q=h(T1-T)
• Solid, q=kSiO2(dT/dx)
– J=q/Hrxn
Grxn<0, Spontaneous
Kinetics
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Thickness
– Linear Rate
• Reaction Control
– First Order
• BL-MT Control
• BL-HT Control
– Parabolic Rate
• Product diffusion Control
• Product heat transfer Control
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J =(dx/dt) SiO2/MW SiO2
Thickness Experiments
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Parabolic Rate
– Derive it!
– dx2/dt=2K
• K=Ko exp(-Ea/RgT)
• x=o @ t=0
• x=  at t= 
– Very common!!
• Slow Solid State
Diffusion
• Slow Heat
Conduction
Mask Thickness
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To effectively prevent ions penetrating in
thick zone
Relatively thick Oxide Protection layer
Patterned
Thinning (etching) of Oxide Protection
layer over implantation zone
Remove oxide layer with impurities inside
Mask Thickness
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Transmission through mask
– T=1/2 erfc[(x-xave)/2 x]
To stop 99.99% of implanted
materials, T=10-4
 Solve for x, the thickness to stop
99.99% of ions.
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SiO2 Mask Thickness
Si3N4 Mask Thickness
Photoresist Mask Thickness
Implantation
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Create Ions in
Vacuum
 Accelerate in
Electric Field
 Impinge onto
Silicon Surface
 Knock out Si ion(s)
– Charge Balance
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Travel deep into
Silicon
Implantation
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Effect of Ion Mass
Implant Depth
Depth Increases with Energy
Implantation Straggle
Increases with Energy
Implantation Concentration
Profile
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Probability Based
 N(x)=Nmax exp[(x-xave)2/2x2]
Nmax=(Ndose/[(2) x])~(0.4 Ndose/ x)
 Ndose=Qdose/e
 Qdose= current applied/cm2
 σx = projected straggle
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Remove Implantation Mask
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Chemical Mechanical Polishing
– Stop etch at the desired thickness of
the Gate Oxide
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Dry Etching
Gate Oxide
Capacitor connecting Gate to center
of npn or pnp heterojunction
 Capacitance
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– Area
– Thickness
– Dielectric constant of oxide
Gate Oxide Capacitance
C=oA/d
=C/Co
=1+e
e =
electric
susceptibility
Metalization
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Transistor Contacts
– Base
– Emitter
– Gate
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Planarize/Polish layer to get Flat
Surface for next lithography Step
Diffusion
Deposition of B or P on surface
 Heat and Hold for period of time
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– Solid State Diffusion
– dC/dt=D d2C/dx2
• C=Co at x=0
• C=0 at x=
– C=Co(1-erf[x/(4Dt)])
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Etch excess B or P from surface
Concentration Profile
1
C xi  1 hr 
C xi  2 hr 
C xi  3 hr 
time
0.5
C xi  4 hr 
0
0
0.5
xi
m
1
Diffusion Coefficient
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Self Diffusion
– D*=Doexp(-Ea/RgT)
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Diffusion of A in B
• Depends on A and matrix B
– DAB =(D*A XB + D*B XA) (d ln [aA]/d ln [XA])
– d ln [aA]/d ln [XA] = 1+ (d ln [A]/d ln [XA])
– d ln [aA]/d ln [XA] ~ 1 for ideal solutions
• And
• DAB =(D*A XB + D*B XA) = (D*A (1-XA) + D*B XA)
• Note Concentration dependence!!
• DAB ~D*A when XA ~0 , the dilute solution limit
– Good for dopants
Implant Depth
Depth Increases with Energy
Diffusion of Implanted Dopants
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Diffusion Furnace or Laser
 Heat Treatment
– Solid State Diffusion
– dCA/dt = CT d/dz (DAB dXA /dz)
• C=Co(z) = CT XA(z) at z=0
• C=0 at z=
– DAB =(D*A XB + D*B XA) (d ln [aA]/d ln [XA])
– Interdiffusion or mutual diffusion coefficient