Transcript Preliminary Design Review Presentation: Data System

Cabin
Pod
Removable Drives
RS-232/422
Display &
Archive PC
2
IF Digitizer
Ethernet
Antenna
Control
CPU
PCI Bus
Data Processing
& Control PC
Ethernet
text
Waveform
Generator
Ethernet
KVM Switch
TX Modulator Control/Status
text
Mult-channel
ADC
125 MHz IF
(to Exciter)
125 MHz IF
(from RX)
TBD
TBD
Reflector Plate Position &
Servo Control
Temp & Pressure Sensor
Inputs
Solid-State Drive
Digital I/O
HIAPER Network
Diagnostic Display &
Keyboard (removable)
IRIG-B I/F
Arinc429 I/F
Aircraft Attitude
Time Code
HIAPER Cloud Radar Data System Drawing
TBD
Interlock (SCR) Control
Signal Processing
•
Use FPGA based commercial (COTS) digital receiver & waveform
generator
– Sub-sample 125 MHz IF @ 100 MHz
– Leverage digtal down converter (DDC) currently under development in EOL
software defined radio (SDR) initiative
– Generate 125 MHz quadrature waveforms required for exciter
•
Send raw I,Q data to in-cabin processor via Ethernet
– Anticipated data rate: 128 Mbits/sec (raw I,Q) or 58 GB/hr
•
Perform spectral processing on all range gates
–
Single 3.6 GHz Pentium 4 should be sufficient based on fftw3 benchmark
@ 20% efficiency (1024 point FFT, 500 range gates, 102.4 msec dwell)
– Generate, display and record “moments” from spectra
– Record limited quantities of timeseries data, disk space a limiting factor