Transcript ppt

ECE 465: Digital Systems
Lecture Notes # 8
Sequential Circuit (Finite-State Machine) Design
SHANTANU DUTT
Department of Electrical and Computer Engineering
University of Illinois, Chicago
Phone: (312) 355-1314: e-mail: [email protected]
URL: http://www.eecs.uic.edu/~dutt
1
Finite State Machine (FSM) Design
• Example : Problem Statement
There is a bit-serial I/P line. Design an FSM that outputs a ‘0’
if an even # of 1’s have been received on the I/P line and the
outputs a ‘1’ otherwise.
• When do we need an FSM (i.e., seq ckt) to solve a problem rather than a
combinational ckt?
• Ans: When the problem requires the design to remember something about
past inputs in order to solve the problem.
• FSMs are different from counters in the sense that they have external I/Ps,
and state transitions are dependent on these I/Ps and the current state.
Note : If a +ve edge triggerred synchronous sequential circuit is being designed,
the counting of the # of 1s (i.e., the sampling of the input(s),
for a general FSM) essentially occurs Tlogic +Tsetup time before every +ve edge.
Sampling
instances
x
Tlogic + Tsetup
O/p y
FSM
CLK
CLK
x
# of even
1s (0)
odd
(1)
even
(2)
odd
(3)
odd
(3)
2
Approach to determining states of an FSM (mainly a “pattern”-recognition FSM
[string, mathematical, etc. patterns] as opposed to an “action” FSM):
• First determine the min # of useful information classes about past i/ps required to solve the
problem (requires analytical thinking about the problem)
• Each info class  a potential state
• From this 1st cut at possible states, determine if there are well-defined transitions from each
state for all possible i/p values.
• If so then these states can be the final states; otherwise some states may need to be refined into
multiple states to achieve well-defined transitions (see FSM word prob. 1).
• In this problem, only 2 classes of information are reqd: whether an even # of 1s have been
received so far, or an odd # of 1s have been received so far & there are well-defined transitions
between them. Thus these 2 classes become 2 states.
Solution 1: (Mealy)
Solution 2: (Moore)
0/0
Reset
Even
Transition
Arc
Reset
Odd
Even
[0]
Input
1/1
1/0
0
Output
O/P is dependent
on current state and
input in Mealy
Output
1
1
Odd
[1]
0
0/1
Mealy Machine: Output is associated with the
state transition, and appears before the state
transition is completed (by the next clock pulse).
Input
Output is
dependent only
on current state
Moore Machine: Output is associated
with the state and hence appears
after the state transition takes place.
Determining a Reset State:
• A reset state is a state the the FSM (seq ckt) should be in when it is just powered on.
• In other words, a reset state is a state the FSM should be in, when it has recvd no i/ps
• Based on the above definition, decide if any of the states determined so far can be a
reset state (i.e., its defn. is consistent w/ not having received any i/p). E.g., in the parity
detector problem, the even state qualifies to be the reset state, as in the reset state no
i/ps recvd  zero 1’s recvd  even # of 1’s recvd  it can be the even state
• If not, then need to have a separate reset state, and have the correct transitions from
this state to the other states (depending on the problem solved by the FSM).
Solution 1: (Mealy)
Solution 2: (Moore)
0
0/0
Reset
Even
Odd
Even
Input
1/1
1/0
Transition
Arc
Reset
Output
Output
[0]
O/P is dependent
on current state and
input in Mealy
1
1
Odd
[1]
0/1
Mealy Machine: Output is associated
with the state transition, and appears
before the state transition is completed
(by the next clock pulse).
0
Input
Output is
dependent only
on current state
Moore Machine: Output is associated
with the state and hence appears
after the state transition take place. 4
External I/Ps
External O/Ps
m1
Comb.
Logic
n even

odd
n
Output
Logic
n
state
= Even
x=1
O/P=0
n
CLK
External Outputs
Moore Machine Model
Mealy Machine Model
Time t : Even I/P
FFs
m2
CLK
t+
Next State
Comb.
Logic
m2
FFs
t
External
I/Ps
m1
 = propagation delay of logic of Mealy M/C
t+TCLK t+TCLK+2
state Moore O/P=1
O/P=1
= Odd
(Mealy)
2 = propagation delay of O/P
logic unit of Moore M/C
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State Transition Table
(Even-Parity Checker)
Encoding: State Variable A, Even State: A = 0 ; Odd State: A = 1.
Present
State
Next
State
Input
Moore
O/P
Mealy
O/P
D-FF
Excit.
y1
y2
DA
T-FF
Excit.
A
x
A+
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
0
1
0
1
1
0
1
0
0
1
Input variables
to comb. logic
Output functions
y2
x
N.S. & O/P
Logic
DA= Ax ; TA= x
y1 = A for Moore
y2 = Ax for Mealy
TA
Q
A FF
x
N.S.
Logic
Or
Q
DA
CLK
A
O/P
Logic
Mealy and Moore Seq.
Circuit Models
FFs
y1
DA
Q Q+ D
0 0
0
0 1
1
1 0
0
1 1
1
Q Q+ T
0 0
0
0 1
1
1 0
1
1 1
0
Excitation tables for a
D-FF and a T-FF
6
Reset
State=0
Even
0
0/0
Reset
State=0
Even
[0]
1/1
1/0
1
1
State=1
Odd
N.S.
Logic
x
State=1
Odd
[1]
Q
0/1
Q
Mealy
0
D-
FF D
Moore
CLK
S.T. is complete.
Assume single bit state information stored in a D-FF
State Transition State Transition
is occurring
is occurring
S.T. is complete.
CLK
x
D
even
Q
odd
even
even
odd
odd
(state)
y2
(Mealy O/P)
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y1
Moore
O/P)
DA= Ax ; TA= x
y1 = A for Moore; y2 = Ax for Mealy
Moore M/C Implementation
a) D-FF
b) T-FF
x
0
D
x=1
Q
R
CLK
A
y1
T
CLK
Q
R
Q
A
y2
Q
Reset
Reset
Moore O/P is synchronized with clock.
Mealy M/C Implementation
a) D-FF
b) T-FF
y1
0
1
D
x=1
CLK
Q
R
x
T
A
CLK
Q
R
y1
Q
Q
Reset
Mealy O/P is not
synchronized with clock.
Reset
Note: Here Moore and Mealy state transition
functions are the same. This will not always be
the case.
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Difference Between Mealy and Moore Machine
Mealy
(1) O/Ps depend on the present
state and present I/Ps
(2) The O/P changes asyn
-chronously with the
enabling clock edge
(3)
(4)
A counter is not a Mealy
machine
A Mealy machine will have
the same # or fewer states
than a Moore machine
Moore
O/Ps depend only on the
present state
Since the O/Ps change
just after the state changes,
and the state change is
synchronous with the
enabling clock edge, O/Ps
change synchronously
with this clock edge
A counter is a Moore
machine (o/ps = state bits)
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Transformations Between Mealy and Moore FSMs
A
B
C
o/ps
00,10 / 00
B
C
00,10
Mealy  Moore
(extra states needed)
11/11
i/ps
01/11
A
11
i/ps
01
o/ps
D
D2
D1
[11]
[00]
Moore
Mealy
A
B
C
o/ps
00,10 / 01
01/01
11/01
i/ps
A
B
Mealy  Moore
(no extra states needed)
C
00,10
01
11
i/ps
o/ps
D
D
[01]
Mealy
•
•
Moore
As can be seen, Mealy  Moore transformation can result in extra states: Mealy states w/
different o/ps in their input transition arcs will need to be replicated in a Moore FSM, w/ the
# of replications = # of different o/ps in the input transitions associated w/ the Mealy state
However, a transformation from Moore  Mealy, will not require any extra state: Each
Moore state becomes a Mealy state w/ its o/p indication moving from the state to all its input
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transition arcs
Another example: A simple vending machine
Here is how the control is supposed to work. The vending machine delivers
a package of gum after it has received 15 cents in coins. The machine has a single
coin slot that accepts nickels and dimes, one coin at a time. A mechanical sensor
indicates to the control whether a dime or a nickel has been inserted into the coin slot.
The controller’s output causes a single package of gum to be released down a chute
to the customer.
One further specification: We will design our machine so it does not give
change. A customer who pays with two dimes is out 5 cents!
Coin
Sensor
Reset
Vending
Machine
FSM
Open
Gum
Release
Mechanism
CLK
Vending Machine block diagram
States:
0C
5C
10C
15C
11
— The figure below show the Moore and Mealy machine state transition diagrams.
( N D  Reset )/0
0 cent
[0]
Reset
ND
0 cent
Reset / 0
N D /0
N/0
N
5 cent
[0]
D
( N D  Reset )/0
Reset / 0
Reset
D/0
D
N
10 cent
[0]
Moore machine
D/1
N/0
ND
10 cent
N D /0
N+D
>=15 cent
[1]
5 cent
N+D/1
>=15 cent
Reset
Reset / 1
Mealy machine
Moore and Mealy machine state diagrams for the vending machine FSM
12
—State transition table for Moore and Mealy M/C (next state col. also gives D-FF
excitation).
Present State
Q1 Q0
0 0
0 1
1 0
1 1
Inputs
Next State
D
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Q 1+
0
0
1
x
0
1
1
x
1
1
1
x
1
1
1
x
N
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q0 +
0
1
0
x
1
0
1
x
0
1
1
x
1
1
1
x
Moore Output Mealy Output
Open
0
0
0
x
0
0
0
x
0
0
0
x
1
1
1
x
Open
0
0
0
x
0
0
1
x
0
1
1
x
1
1
1
x
Q+ = D
Q Q+
0 0
0 1
1 0
1 1
Encoded vending machine state transition table. Note: Do not have to design
for the reset input if FFs have a direct reset inputs. Make sure though that reset state is
encoded as all 0’s if possible; otherwise need FFS w/ asynch. reset as well as set inputs
D
0
1
0
1
13
Implementation using D-FFs
Q1Q0
Q1Q0
00
01
11
10
00
0
0
1
1
01
0
1
1
11
x
x
10
1
1
DN
Q1Q0
00
01
11
10
00
0
1
1
0
1
01
1
0
1
x
x
11
x
x
1
1
10
0
1
K-map for D1
DN
00
01
11
10
00
0
0
1
0
1
01
0
0
1
0
x
x
11
x
x
x
x
1
1
10
0
0
1
0
DN
K-map for Open (Moore)
K-map for D0
Q1Q0
D1 = Q1 + D + Q0·N
D0  N  Q0  Q0  N  Q1  N  Q1  D
OPEN = Q1·Q0
Moore OPEN = Q1·Q0 + D·Q0 + D·Q1 + N·Q1
00
01
11
10
00
0
0
1
0
01
0
0
1
1
DN
11
x
x
x
x
10
0
1
1
1
Mealy
K-map for Open (Mealy)
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Q1
D1
D
D
Q0
N
Q1
CLK
Q
R
Q1
Q
OPEN
Reset
N
Q0
Similarly, a Mealy
implementation;
only the OPEN
function changes.
Q0
D0
N
Q1
D
CLK
Q
R
Q
Q0
Q0
N
Reset
Q1
Input transition logic cost = 17 (total gate i/ps)
D
Vending machine FSM implementation based on D flip-flops(Moore).
15
Implementation using J-K FFS
J-K Excitation
D N
Q 1+ Q0+
J1 K 1 J0 K 0
Q Q+
0 0
0
0
0 x
0 x
0 1
0
1
0 x
1 x
0 0
1 0
1
0
1 x
0 x
0 1
1 1
x
x
x x
x x
1 0
0 1
0 0
0
1
0 x
x 0
1 1
0 1
1
0
1 x
x 1
1 0
1
1
1 x
x 0
1 1
x
x
x x
x x
1 0
0 0
1
0
x 0
0 x
0 1
1
1
x 0
1 x
1 0
1
1
x 0
1 x
1 1
x
x
x x
x x
1 1
0 0
1
1
x 0
x 0
0 1
1
1
x 0
x 0
1 0
1
1
x 0
x 0
1 1
x
x
x x
x x
Remapped next-state functions for the vending machine example.
Q1 Q0
0 0
J
0
1
x
x
16
K
x
x
1
0
Q1Q0
00
01
11
10
00
0
0
x
x
01
0
1
x
11
x
x
10
1
1
DN
Q1Q0
00
01
11
10
00
x
x
0
0
x
01
x
x
0
0
x
x
11
x
x
x
x
x
x
10
x
x
0
0
DN
K-map for J1
K-map for K1
Q1Q0
Q1Q0
00
DN
00
01
0
1
01
11
10
x
x
0
x
x
1
00
01
11
10
00
x
0
0
x
01
x
1
0
x
DN
11
x
x
x
x
11
x
x
x
x
10
0
x
x
1
10
x
0
0
x
K-map for J0
K-map for K0
K-maps for J-K flip-flop implementation of vending machine.
J1 = D + Q0·N
J 0  Q0  N  Q1  D
K1 = 0
K 0  Q1  N
17
N
Q0
CLK
D
Q0
J
Q
K R
Q
Q1
Q1
OPEN
N
Q1
D
CLK
Q1
J
Q
K R
Q
Q0
Q0
N
Reset
Input transition logic cost = 12 (total gate i/ps), much less
than using D-FFs (17) due to the numerous X’s in the
excitation function of a J-K that combinational logic
synthesis can use to minimize function cost
J-K flip-flop implementation for the vending machine example (Moore).
Similarly, a Mealy implementation; only the OPEN function changes.
18
Basic Steps in the FSM Design Procedure
(1-3 mainly for pattern-recognition FSMs)
1. Understand the problem and determine the minimal # of different information
classes about past i/ps required to solve it.
2. Convert these information classes into distinct states (which we informally call
tentative states), and determine the state transition diagram of the FSM.
3. If the state transitions between states are well-defined (i.e., for each state and i/p
value, it is unambiguous what the next state should be), then these are the final
states.
• Otherwise, states from which transitions are not well defined need to be
broken into multiple states (called extra states) so that non-well-defined
transitions are then translated to well-defined transitions between the original
state(s) that did not have all transitions well-defined, and the extra state(s), and
also from the extra state(s) to other original states (see, e.g., FSM prob. 1 next)
4. Determine the reset state
5. Perform state minimization
6. (a) Encode states in binary [optional—perform state assignment for logic
minimization] & obtain state transition table &FF excitation for desired FF type. Or
(b) Implement a one-hot style seq. ckt in which each state is repr. by a unique FSM
7. Minimize the FF input functions (using K-Maps or QM, for example) and
implement the FSM using these FFs and logic gates (or MUXes, PLAs, PALs, etc.)
that implement the FF’s input functions.
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FSM Word Problem 1:
• Design a system that outputs a ‘1’ whenever it receives a multiple
of 3 # of 1’s (i.e., 0, 3, 6, 9, etc. # of 1’s) on a serial input line x.
— Relevant information classes needed to solve the problem:
(A) A multiple of 3 # is received.
(B) A non-multiple of 3 # is received.
Questions to consider:
(1) How do we go from (A)(B)
Ans.: If a ‘1’ is received
(2) How do we go from (B)(A)
Ans.: Not clear. Need to split up (B) further into
(B1): 3y+1 # of 1’s received.
Where y is an integer  0.
(B2): 3y+2 # of 1’s received.
20
Note: (A): is 3y+0 = 3y # of 1’s received.
• Now the transitions between the3 classes of information is clear:
(A)  (B1)  (B2)  (A)
1 received
1 received
1 received
• Hence these classes of information can be considered states of
the required as states of the required FSM:
These 3 states can be represented by 3y+I, i = 0,1,2
00
Reset
0/1
i=0
0
Output
Input
Reset
i=0
[1]
0/0
1/0
1/1
10
01
i=1
1/0
i=2
0/0
Mealy Machine
1
1
0
i=1
[0]
i=2
[0]
1
0
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Moore Machine
FSM Word Problem 2:
• Design a system that outputs a ‘1’ whenever it receives:
(a) A multiple of 3 # of 1’s AND (b) A non-zero even # of 0’s
# of 1’s
E.g., ((0,2) , (3,2) , (3,4) , (6,2) ,···)
# of 0’s
— Relevant classes of information: Use D&C to figure this out!
- Break problem into relevant classes of # of 1’s & relevant
classes of # of 0’s
- For # of 1’s: 3y+i, i = 0,1,2
[3 classes]
- For # of 0’s: 2z+j, j = 0,1
For j = 0, we need to distinguish between zero (z = 0)
and non-zero (z > 0) # of 0’s
- Thus we have 3 classes:
2z+0, z = 0 ( 0 )
2z+0, z > 0 ( non-zero even )
22
2z+1
( odd )
The relevant # of 1’s can be represented by i = { 0, 1, 2 }
( # of 1’s = 3y+i )
— The relevant # of 0’s can be represented by j= { 00 , 0>0 , 1 }
( # of 0’s = 2z+j ) where the subscript of the 0 indicates whether
z=0 or z>0.
— Since at any point time, a certain # of 1’s and # of 0’s will have
been received, the state of the system will be given by
a combination of relevant # of 1’s and # of 0’s.
— There are 9 combinations:
{ 0, 1, 2, } X { 00, 0>0, 1 } = (0,00), (0,0>0), (0,1), (1,00), (1,0>0),
(1,1), (2,00), (2,0>0), (2,1) 
# of 1’s
# of 0’s
Cartesian
Product
23
(0,00)
(0,0>0)
(1,00)
(0,1)
(2,00)
(1,1)
(2,1)
(1,0>0)
(2,0>0)
24
Note: 0>0  2z+j, j = 0
z>0
Reset
(0,00)
1/0
0/0
1/0
(0,0>0)
(1,00)
1/0
0/0
0/0
0/1
1/0
(0,1)
(2,00)
0/0
(1,1)
0/0
1/0
1/0
0/0
(2,1)
(1,0>0)
1/1
0/0
1/0
0/0
(2,0>0)
1/0
25
Interacting FSMs
• Another option is to have 2 independent FSM’s one for detecting the desired
# of 1’s and another for the desired # of 0’s. The o/p of the combined machine
is 1 when both FSM’s are in states w/ o/p = 1
For # of 0’s: 2z+j, j = 0,1
For j = 0, we need to distinguish between zero (z = 0) &
non-zero (z > 0) # of 0’s
[3 classes]: FSM2
1
Reset
j=0
z=0
0
1
[0]
0
For # of 1’s: 3y+i, i = 0,1,2
[3 classes]: FSM1
0
Reset
• Each pair of
states of the 2
FSMs  a
state of the
composite
fsm (previous
design)
i=0
[1]
1
1
i=2
[0]
j=1
[0]
0
i=1
[0]
x
j=0
z>0
[1]
1
FSM1
o/p1
AND
• Do we save on FFs here?
y
• What about the general case (in
which we divide an FSM w/ m1*m2 states into 2
FSMs, one w/ m1 and the 2nd w/ m2 states ?
• Do we save on logic (here and in general)?
0
FSM2
o/p2
1 state pair; there are 9, and
each pair (S1,i, S2,j) represents
that state of the entire system
(the 1,2 in the state subscript
represents the fsm and i, j the
state within the fsm).
26
Interacting FSMs (contd)
Reset
i=0
• Each pair of
[1]
states of the 2
FSMs  a
1
state of the
composite fsm
(previous
i=2
design)
[0]
0
Reset
1
0
1
j=0
z=0
[0]
0
1
0
i=1
[0]
j=1
[0]
x
1
FSM1
FSM2
o/p1
o/p2
AND
j=0
z>0
[1]
0
1
a state pair
y
• Q: When can a single FSM design be decomposed into >= 2 simpler interacting fsm’s?
• Answer:
1. When the compound o/p condition can be decomposed into multiple smaller o/p conditions
joined together by some logical operations (as in this example). In such a case, these smaller
conditions can each be determined by a simpler fsm. Each of these simpler fsm’s o/ps are used
to determine the final o/p via extra logic depending on how the multiple smaller o/p conditions
are logically “connected” to form the original o/p condition.
2. Or, in general, if we can use D&C to decompose the problem into smaller sub-problems
(which may not all be the same type) and stitch them up, as we saw for the D&C of
combinational circuits. E.g., problem: System needs to o/p a 1 when a multiple of 6 1’s has
27
been seen. Can this be decomposed into smaller problems?