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Energy-Efficient Address Translation
Vasileios Karakostas, Jayneel Gandhi, Adrian Cristal,
Mark D. Hill, Kathryn S. McKinley, Mario Nemirovsky,
Michael M. Swift, Osman S. Unsal
Executive Summary
Problem: TLBs consume energy, especially hits
Energy-Efficient Address Translation
Insight: Increased TLB reach reduces TLB pressure
Lite mechanism: selectively resize L1 TLB resources to save energy
TLBLite design: commodity processors with huge pages
RMMLite design: RMM with support for range translations [ISCA’15]
Results
23% - 71% reduction in address translation energy
2
Outline
Motivation + Opportunity
Energy-Efficient Address Translation
Results
3
Virtual Memory is not free
Performance overhead due to page walks – previous work
Energy overhead due to TLB lookups
On every memory operation
> 90% in L1 TLBs
4%
9%
13%
21%
TLBs
6%
This work
Leverage TLB reach to
improve energy-efficiency
45%
Fetch+Decode
OOO+Speculation
Integer Execution
Caches
TLBs
Legacy
Others
4
*Sodani’s/Intel keynote at MICRO 2011
Base 4KB Pages
Core
Hit
Per-core TLB hierarchy
Focus on data TLBs
Miss
L1 TLB
L2 TLB
Miss  Page Walk
Page Table Walker
5
Base 4KB Pages
Core
Performance overhead
Up to 50% in page walks
L1 TLB
Energy overhead
L2 TLB
60% in L1 TLB accesses
35% in page walks
Page Table Walker
6
Huge Pages
Core
4KB TLB
L1 TLB
2MB TLB
L2 TLB
Page Table Walker
7
Huge Pages
Core
Performance improves, but..
Energy
increases by 4%
2MB TLB
4KB TLB
L2 TLB
Separate L1 TLBs
Up to 43% increase
91% of energy  L1 TLBs
Page Table Walker
8
Redundant Memory Mappings [ISCA ’15]
Virtual Memory
Physical Memory
Range Translations
Arbitrarily-large mappings between contiguous virtual pages to
contiguous physical pages with uniform protection
9
Redundant Memory Mappings [ISCA ’15]
Core
4KB TLB
2MB TLB
L2 TLB
L2 range TLB
10
Redundant Memory Mappings [ISCA ’15]
Core
4KB TLB
L2 TLB
Performance improves a lot
Increases L2 TLB reach
Eliminates page walks
2MB TLB
Energy
still
L2
range TLB
high
The “innocent” L1 TLB hits!
98% of energy in L1 TLBs
11
State of the art
4KB Pages
Huge Pages
RMM
Performance
Dynamic Energy
Our goal: improved performance and reduced energy
12
Key Observation
Can we leverage increased TLB reach to save energy?
Yes! Naturally take pressure off L1 TLBs
Core
Why access all
L1 TLB entries,
esp. for 4KB
pages?
4KB TLB
2MB TLB
• Look up fewer entries
• Reduce dynamic
L2 TLB energy
• Similar performance
Larger Reach
Single 2MB entry
==
512 x 4KB entries
13
Outline
Motivation + Opportunity
Energy-Efficient Address Translation
1. The Lite mechanism
2. TLBLite design for huge pages
3. RMMLite design for range translations
Results
14
The Lite Mechanism
Goal: Save TLB energy with similar performance
Utility-based monitoring [Drophso et al. PACT ’02, Qureshi et al. MICRO ’06]
Distance of TLB hits from MRU position
Inferring utility of active ways
Way disabling
15
The Lite Mechanism
C0 1
0
MRU
C1 0
page 10
page 30
page 90
LRU
page 50
MRU
page 35
C2 0
L1 TLB distance counters
SET 0Track distance of hits
Monitor utility
C0  distance 0
distance
== 0 1
C1  distance
C2  distance 2-3
page 35
page 25
page 55
LRU
page 75
SET 1
16
The Lite Mechanism
C0 1
MRU
C1 0
1
page 10
page 30
page 90
LRU
C2 0
SET 0
page 50
distance == 1
page 30
MRU
page 35
page 25
page 55
LRU
page 75
SET 1
17
The Lite Mechanism
C0 95
MRU
C1 46
...
...
...
After many
TLB accesses
(interval ends)
LRU
...
MRU
...
...
...
LRU
C2 2
...
SET 0
Ways 2-3 less useful
Disable them
[Albonesi, MICRO’99]
SET 1
18
The Lite Mechanism
C0 0
MRU
C1 0
C2 0
...
...
...
LRU
...
MRU
...
SET 0
Save energy on
every TLB lookup
page XY
...
...
LRU
...
SET 1
19
TLBLite design
Core
4KB TLB
2MB TLB
Lite
Lite
L2 TLB
20
RMMLite design
Core
4KB TLB
L1
2MB
range
TLBTLB
Lite
High hit ratio
L2 range TLB
L2• TLB
Fewer L1 TLB misses
• Disables more ways
21
RMMLite design
L1-range TLB
Core
4KB TLB
Lite
L2 TLB
small but efficient (4 entries)
arbitrarily-large
L1 range TLB mappings
Virtual Memory
L2 range TLB
Physical Memory
22
Outline
Motivation + Opportunity
Energy-Efficient Address Translation
Results
23
Methodology
Developed MMU Simulator
– Pin, Cacti, and profiling with Linux Pagemap
– Baseline: Intel Sandy Bridge
Dynamic energy & performance models
– For the address translation path
TLB intensive workloads
– Spec2006, BioBench, and Parsec
24
Miss Cycles
Energy
120%
L1 TLB misses
L2 TLB misses
100%
100%
80%
80%
Cycles spent in
address translation
60%
40%
60%
40%
20%
20%
0%
0%
4KB
2MB
TLB-Lite
L1 4KB TLB
L2 4KB TLB
RMM-Lite
L1 range TLB
Page walks
Dynamic energy spent
in address translation
Geometric mean
4KB
2MB
(detailed results in paper)
RMM
L1 2MB TLB
L2 range TLB
TLB-Lite
RMM
RMM-Lite
25
(normalized to)
Miss Cycles
4KB
120%
L1 TLB misses
L2 TLB misses
Energy
L1 4KB TLB
L2 4KB TLB
L1 2MB TLB
L2 range TLB
L1 range TLB
Page walks
100%
100%
L1 TLB
80%
80%
64 entries, 4-way
60%
L2 TLB
60%
40%
512 entries,
4-way
40%
20%
20%
0%
0%
4KB
2MB
TLB-Lite
RMM
RMM-Lite
High performance overhead
page walks
4KB
2MB
TLB-Lite
RMM
RMM-Lite
High energy overheads
60% in L1 TLB
35% in page walks
26
Miss Cycles
2MB
120%
L1 TLB misses
L2 TLB misses
Energy
L1 4KB TLB
L2 4KB TLB
L1 2MB TLB
L2 range TLB
L1 range TLB
Page walks
100%
100%
80%
4KB configuration
60%
+ L1 2MB TLB
80%
60%
32 entries,
40%4-way
40%
20%
20%
0%
0%
4KB
2MB
TLB-Lite
RMM
RMM-Lite
4KB
2MB
TLB-Lite
RMM
RMM-Lite
Energy increases
Performance improves, but..
4% on average and up to 43%
Separate L1 TLBs
27
Miss Cycles
TLBLite
120%
L1 TLB misses
L2 TLB misses
100%
100%
80%
80%
Energy
L1 4KB TLB
L2 4KB TLB
L1 2MB TLB
L2 range TLB
L1 range TLB
Page walks
2MB configuration
60%
+ Lite
60%
40%
40%
20%
20%
0%
0%
4KB
2MB
TLB-Lite
RMM
RMM-Lite
4KB
2MB
TLB-Lite
RMM
RMM-Lite
Reduces energy by 23%
Similar performance with 2MB
49% of lookups with fewer than
28
4 ways in L1 4KB TLB
Miss Cycles
RMM [ISCA ’15]
120%
L1 TLB misses
L2 TLB misses
Energy
L1 4KB TLB
L2 4KB TLB
L1 2MB TLB
L2 range TLB
L1 range TLB
Page walks
100%
100%
80%
2MB configuration
60%
+ L2 range TLB
80%
60%
32 entries,
40%fully assoc.
40%
20%
20%
0%
0%
4KB
2MB
TLB-Lite
RMM
RMM-Lite
Even better performance, but..
4KB
2MB
TLB-Lite
RMM
RMM-Lite
Energy is still high
Similar to 2MB pages  L1 TLBs29
Miss Cycles
RMMLite
120%
L1 TLB misses
L2 TLB misses
Energy
L1 4KB TLB
L2 4KB TLB
L1 2MB TLB
L2 range TLB
L1 range TLB
Page walks
100%
100%
RMM configuration
80%
+ L1 range TLB
60%
80%
60%
4 entries, fully assoc.
40%
+ Lite
40%
20%
20%
0%
0%
4KB
2MB
TLB-Lite
RMM
RMM-Lite
Better performance vs. RMM
Fewer L1 TLB misses
4KB
2MB
TLB-Lite
RMM
RMM-Lite
Reduces dynamic energy by 71%
84% of hits from L1 range TLB
30
63% of lookups with 1 way in 4KB
Summary
4KB
pages
Huge
pages
TLBLite
RMM
RMMLite
Performance
Dynamic
Energy
23%
71%
Observation: Increased TLB reach reduces TLB pressure
31
Thank you!
32
BACKUP
SLIDES
33
Summary
Problem: TLBs consume energy, especially hits
Energy-Efficient Address Translation
Insight: Increased TLB reach reduces TLB pressure
Lite mechanism: selectively resize L1 TLB resources to save energy
TLBLite design: commodity processors with huge pages
RMMLite design: RMM with support for range translations [ISCA’15]
Results
23% - 71% reduction in address translation energy
34
Related Work
Optimizing TLBs for energy-efficiency
– Circuit techniques [ISLPED ’97]
– Partitioning TLBs [ISLPED ’03, CASES ’06, ISLPED ’13]
– Filtering TLB requests [ISLPED ’05, TVLSI ’07]
Dynamically resizing TLB [MICRO ’00]
– Single reference bit per TLB entry
– Targets monolithic TLB
Selective TLB lookups [MICRO ’02, ISPASS ’04, CODES ’04]
– Compiler support and special registers
35
Related Work
TLB-Pred [HPCA ’15]
– All page sizes into single set-associative TLB
– See paper for comparison
Virtual caches
– Defer address translation until cache miss
– Increase hardware complexity (synonyms, protection)
36
Cycles Spent in TLB misses (%)
0.0001
0.0166
2.0E-06
0.0453
2.0E-06
0.2302
1.3523
0.0022
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
0%
0.0040
20%
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
Miss Cycles Overhead: TLB Intensive Workloads
L1 TLB misses
canneal
geomean
astar
cactusADM
GemsFDTD
mcf
L2 TLB misses
100%
80%
60%
40%
omnetpp
zeusmp
mummer
37
astar
cactusADM
GemsFDTD
mcf
omnetpp
zeusmp
mummer
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
L2-range TLB
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
L2-4KB TLB
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
L1-range TLB
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
L1-2MB TLB
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
L1-4KB TLB
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
4KB
THP
TLB-Lite
RMM
TLB-PP
RMM-Lite
Dynamic Energy (%)
Energy Overhead: TLB Intensive Workloads
140%
Page walks
120%
100%
80%
60%
40%
20%
0%
canneal
geomean
38
Miss Cycles and Energy Overheads: Spec2006
L1 TLB misses
L2 TLB misses
200%
100%
80%
L1 4KB TLB
L2 4KB TLB
L1 2MB TLB
L2 range TLB
L1 range TLB
Page walks
150%
60%
100%
40%
50%
20%
0%
4KB
2MB
TLB-Lite
RMM
RMM-Lite
0%
4KB
2MB
TLBLite and RMMLite reduce the
dynamic energy by 26% and 72%
TLB-Lite
RMM
RMM-Lite
39
Miss Cycles and Energy Overheads: PARSEC
L1 TLB misses
L2 TLB misses
200%
100%
80%
L1 4KB TLB
L2 4KB TLB
L1 2MB TLB
L2 range TLB
L1 range TLB
Page walks
150%
60%
100%
40%
50%
20%
0%
4KB
2MB
TLB-Lite
RMM
RMM-Lite
0%
4KB
2MB
TLBLite and RMMLite reduce the
dynamic energy by 20% and 66%
TLB-Lite
RMM
RMM-Lite
40
Percentage of L1 TLB lookups with active ways
TLBLite
RMMLite
4-ways
2-ways
1-way
4-ways
2-ways
1-way
4KB
51.2%
32.9%
15.9%
25.9%
10.4%
63.7%
2MB
81.1%
9.0%
9.9%
-----
41
Distribution of L1 TLB hits
TLBLite
RMMLite
4KB
2MB
4KB
Range
15.9%
35.6%
15.9%
84.1%
42
Comparison with TLB-Pred [HPCA ’15]
L1 TLB misses
L1 4KB TLB
L2 4KB TLB
L2 TLB misses
60%
40%
20%
L1 range TLB
Page walks
120%
100%
80%
L1 2MB TLB
L2 range TLB
100%
Same as 2MB
80% conf.
• Perfect 60%
prediction
• Both L140%
and L2 TLB
hold 4KB
20%and 2MB pages
0%
0%
Improved performance
• Energy reduces vs. 2MB conf.
• Still, RMMLite more energy-efficient
43
• Orthogonal to range translations
Impact of Eager Paging
L1 TLB misses
L2 TLB misses
120%
100%
L1 4KB TLB
L2 4KB TLB
L1 2MB TLB
L2 range TLB
L1 range TLB
Page walks
100%
80%
80%
60%
60%
40%
40%
20%
20%
0%
4KB
RMM-Lite
RMM-Lite-EP
0%
4KB
RMM-Lite
RMM-Lite-EP
44