Transcript ppt

TLC: Transmission Line
Caches
Brad Beckmann
David Wood
Multifacet Project
http://www.cs.wisc.edu/multifacet/
University of Wisconsin-Madison
12/3/03
Overview
• Problem: Global interconnect
• Opportunity: On-chip transmission lines
– What are they?
– Why now?
• Application: Large on-chip caches
• Solution: TLC: Transmission Line Caches
+
+
+
–
–
Consistent high performance
Simple logical design
Less substrate area
Circuit verification
Wafer manufacturing cost
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Outline
•
•
•
•
•
•
Problem: Global interconnect
Opportunity: On-chip transmission lines
Application: Large on-chip caches
Solution: TLC: Transmission Line Caches
Evaluation
Conclusions
Beckmann & Wood
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Global Interconnect Problem
• Global interconnect latency → Bottleneck
– RC delay dominant
– Held constant using repeaters
– Doesn’t scale with transistors
• Large structures particularly hurt
– Partitioning mitigates intra-partition delay
– Performance dominated by inter-partition delay
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Conventional Solution
• ↑ wire size → ↓ RC delay
+ 3x size → 3x reduced delay
+ ↑ wire segment length
– 3x channel area
– Doesn’t scale
• Intrinsic repeater delay
• Inductive effects
A Better Solution?
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Outline
•
•
•
•
•
•
Problem: Global interconnect
Opportunity: On-chip transmission lines
Application: Large on-chip caches
Solution: TLC - Transmission Line Caches
Evaluation
Conclusions
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RC vs. TL Communication
Conventional Global RC Wire
Voltage
Voltage
Vt
Distance
Driver
Receiver
On-chip Transmission Line
Voltage
Voltage
Vt
Distance
Driver
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Receiver
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RC Wire vs. TL Design
Conventional Global RC Wire
~0.375 mm
RC delay dominated
On-chip Transmission Line
~10 mm
Driver
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LC delay dominated
MICRO ’03 - TLC: Transmission Line Caches
Receiver
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On-chip Transmission Lines
• Why now? → 2010 technology
– Relative RC delay ↑
– Improve latency by 10x or more
• What are their limitations?
– Require thick wires and dielectric spacing
– Increase wafer cost
Presents a different Latency/Bandwidth Tradeoff
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Latency Comparison
Latency (cycles)
(cycles)
Latency
Link Latency
50
50
40
40
RepeatedRC
RC
Repeated
30
30
SingleTL
TL
Single
20
20
10
10
00
0.5
1.5 22 2.5
2.5 33
0.5 1 1.5
Length (cm)
(cm)
Length
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Bandwidth Comparison
2 transmission line signals
50 conventional signals
Key observation
• Transmission lines – route over large structures
• Conventional wires – substrate area & vias for repeaters
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Outline
•
•
•
•
•
•
Problem: Global interconnect
Opportunity: On-chip transmission lines
Application: Large on-chip caches
Solution: TLC: Transmission Line Caches
Evaluation
Conclusions
Beckmann & Wood
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Texas Non-uniform Cache
Architectures (NUCA)
Request 0x….C
0x….3
Bank
Cache
Controller
Switch
SNUCA – statically partitions addresses across the banks
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Texas DNUCA Solution
Issues with DNUCA
A
B
• Locating cache blocks
• Power consumed
accessing distant banks
• 15% of total area
devoted to routing
channels
Frequently requested blocks migrate towards the cache controller
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Outline
•
•
•
•
•
•
Problem: Global interconnect
Opportunity: On-chip transmission lines
Application: Large on-chip caches
Solution: TLC - Transmission Line Caches
Evaluation
Conclusions
Beckmann & Wood
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TLC - Transmission Line Cache
TL Drivers &
Receivers
TL link
2x8 bytes
512 KB
Bank
TLC Cache
Controller
High bandwidth, low latency interface between the controller and banks
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TLC Cache Controller
Transmission Lines
Repeaters
Latches
Multicycle
delay
Transmission
Lines
Transmission
Line
Transceivers
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Central
Cache
Controller
Logic
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Outline
•
•
•
•
•
•
Problem: Global interconnect
Opportunity: On-chip transmission lines
Application: Large on-chip caches
Solution: TLC - Transmission Line Caches
Evaluation
Conclusions
Beckmann & Wood
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Methodology
• Assumptions
– ITRS projection for 2010
• 45 nm technology
• Low-k (2.1) intermetal dielectric
– 10 GHz operational frequency
• Physical Evaluation
– Linpar RLC extractor
– Hspice W element transmission line
• Performance Evaluation
– Full system simulation
– Simics extended with an Out-of-Order processor and
memory system timing models
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Cache Characteristics
Cache
Design
Total
Size
Banks Bank Size Bank Access Uncontended
Time
Latency
SNUCA
16 MB 32
512 KB
8 cycles
9 – 32 cycles
DNUCA
16
256
64
3
3 – 47
TLC
16
32
512
8
10 – 16
• Exclusive write-back caches
• 4 wide, 30 stage pipeline, OoO processor
• 300 cycle memory latency
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Normalized Execution Time
Time
Performance
11
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.6
0.5
0.5
SNUCA
DNUCA
0.4
0.4
TLC
0.3
0.3
0.2
0.2
0.1
0.1
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SpecINT
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Benchmarks
SpecFP
Commercial
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Substrate Area
Cache
Design
Storage
Area
Channel
Area
Controller Total
Area
Area
D-NUCA 92 mm2
17 mm2
1.1 mm2
110 mm2
TLC
3.1
10
91*
77
* 18% reduction
• On-chip transmission lines allow direct routing from
the driver to receiver without repeaters
• Facilitates compact layout
• Devotes less substrate area to the routing channels
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Link Utilization (%)
Link Utilization
2
TLC
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Benchmarks
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Optimized TLC Designs
• Utilize fewer transmission lines
– Base design: requires 2k transmission lines
– Opt designs: require 1k, 500, & 350
• Reduce manufacturing cost
• Increase logic complexity
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Link Utilization
Utilization (%)
Link
(%)
Link
Utilization
(%)
Link Utilization (TLC Family)
14
14
12
12
10
10
88
8
6
66
44
4
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TLC
TLC
TLC
TLC
TLCopt
TLCopt 1000
1000
TLCopt
TLCopt 500
TLCopt
TLCopt 350
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2
2
00
0
0
Benchmarks
Benchmarks
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Normalized Execution Time
Performance (TLC Family)
1
0.8
TLC
0.6
TLCopt 1000
TLCopt 500
0.4
TLCopt 350
0.2
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Benchmarks
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Conclusions 1
• Transmission lines offer a different
latency/bandwidth tradeoff
• Advantages
– Lower latency for global links
– Direct routing over large structures
• Limitations
– Large, sparsely populated, metal layers
– Greater circuit verification effort
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Conclusions 2
• Possible application: TLC
• Advantages
– Consistent high performance
– Simpler logical design
– 18% less substrate area
– Less power in the communication network
• Disadvantages
– Circuit verification
– Wafer cost
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Other Applications?
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Optimized TLC Designs
TLCopt 1000
• Blocks are partitioned
across 2 banks
TL link
2x64
2x44
2x126bits
bits
• Each transmission line
link is 126 bits wide
• 1008 total data TLs
TLCopt 500
1 MB
Bank
• Blocks are partitioned
across 4 banks
• Each transmission line
link is 64 bits wide
• 512 total data TLs
TLCopt 350
TLCopt Cache
Controller
• Blocks are partitioned
across 8 banks
• Each transmission line
link is 44 bits wide
• 352 total data TLs
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Equake Performance
Executed Cycles
8
7
6
5
4
3
2
1
0
Cycles
Misses per 1K Instr.
Misses per 1K Instructions
TLC
LRU
TLC 4way
TLC 8- TLC 16- TLC 32- DNUCA
way
way
way
7.E+08
6.E+08
5.E+08
4.E+08
3.E+08
2.E+08
1.E+08
0.E+00
C
TL
LR
U
C
TL
y
wa
4
Cache Design
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C
TL
y
wa
8
C
TL
ay
w
16
A
ay
C
w
U
32
DN
C
TL
Cache Design
31
Additional Transceiver Delay
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