Transcript ppt
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 29: November 10, 2014 Memory Core: Part 1 1 Penn ESE370 Fall2014 -- DeHon Today • 5T/6T SRAM – Writing – Charge sharing – Precharge • DRAM 2 Penn ESE370 Fall2014 -- DeHon Memory Bank 3 Penn ESE370 Fall2014 -- DeHon 5T SRAM Memory Bit 4 Penn ESE370 Fall2014 -- DeHon Write (preclass 1) • Assuming properly select only one WL, what does write circuit look like? – What transistors are ON when writing a 0 over a cell that holds a 1? – Drive with inverter at BL • Width Wwrite 1V – Voltage written? 5 Penn ESE370 Fall2014 -- DeHon Write (preclass 1) • Assuming properly select only one WL, what does write circuit look like? – Voltage written? Raccess Rwrite Raccess Rwrite Rbuf 1V 1 Penn ESE370 Fall2014 -- DeHon 1 W access W write 1 1 1 W access W write W buf 6 Write Conclude? • Writing into cell is a ratioed operation. 1 1 W access W write 1 1 1 W access W write W buf 7 Penn ESE370 Fall2014 -- DeHon Write (preclass 2) • Assuming properly select only one WL, what does write circuit look like? – How different when writing a 1 over a cell holding a 0 ? 1V 8 Penn ESE370 Fall2014 -- DeHon 6T Cell • How does 6T make it easier to perform writes? 9 Penn ESE370 Fall2012 -- DeHon Preclass 3 • Initially – A @ 1V – B @ 0V • Close switch • Voltage at A? 10 Penn ESE370 Fall2014 -- DeHon Preclass 3 Initially – A @ 1V – B @ 0V • QA=1V*C1=C1 Close switch • Qtot=Vfinal*(C1+C0) • Charge conservation – QA=Qtot • C1=Vfinal*(C1+C0) Penn ESE370 Fall2014 -- DeHon C1 V final C1 C0 11 Consider (preclass 4) • Read: What happens to voltage at A when WL turns from 01? – Assume Waccess large – Waccess >> Wpu=1 – BL initially 0 – A initially 1 12 Penn ESE370 Fall2014 -- DeHon Voltage After enable Word Line • • • • QBL = 0 QA = (1V)(g(2+Waccess)C0) CBL>>CA=(g(2+Waccess)C0) After enable Waccess (Waccess large) – Total charge QBL +QA roughly unchanged – Distributed over larger capacitance~=CBL – VA=VBL~= CA/CBL 13 Penn ESE370 Fall2014 -- DeHon Larger Resistance? • What happens if Waccess small? – Waccess < Wpu 14 Penn ESE370 Fall2014 -- DeHon Larger Resistance? • What happens if Waccess small? – Waccess < Wpu • Takes time to move charge from A to BL • Moves more slowly than replished by pu 15 Penn ESE370 Fall2014 -- DeHon Simulation: Waccess=100 16 Penn ESE370 Fall2014 -- DeHon Simulation 17 Penn ESE370 Fall2014 -- DeHon Charge Sharing • Conclude: charge sharing can pull down voltage 18 Penn ESE370 Fall2014 -- DeHon Consider • What happens to voltage at A when WL turns from 01? – Assume Waccess large 19 Penn ESE370 Fall2014 -- DeHon Simulation Waccess=20 20 Penn ESE370 Fall2014 -- DeHon Simulation Waccess=4 21 Penn ESE370 Fall2014 -- DeHon Charge Sharing • Conclude: charge sharing can lead to read upset – Charge redistribution adequate to flip state of bit 22 Penn ESE370 Fall2014 -- DeHon How might we avoid? 23 Penn ESE370 Fall2014 -- DeHon Charge to middle Voltage • Charge bitlines to Vdd/2 before begin read operation • Now charge sharing doesn’t swing to opposite side of midpoint 24 Penn ESE370 Fall2014 -- DeHon Pre-Charge • Use one phase of clock to charge a node to some initial value before operation Precharge Transistor Can be large 25 Penn ESE370 Fall2014 -- DeHon Simulation Waccess=20 26 Penn ESE370 Fall2014 -- DeHon Compare • Both Waccess=20; vary precharge 27 Penn ESE370 Fall2014 -- DeHon Simulation Waccess=20 (precharge Vdd/2, reading 0) 28 Penn ESE370 Fall2014 -- DeHon Simulation Waccess=20 (with precharge Vdd/2) 29 Penn ESE370 Fall2014 -- DeHon Pre-Charge • Use one phase of clock to charge a node to some initial value before operation Precharge Transistor Can be large 30 Penn ESE370 Fall2014 -- DeHon 5T/6T SRAM Questions? 31 Penn ESE370 Fall2014 -- DeHon Idea • Memory can be compact • Demands careful sizing 32 Penn ESE370 Fall2014 -- DeHon Admin • HW7 due tomorrow • Project 2 out – Due 2 weeks from tomorrow • Tuesday before Thanksgiving 33 Penn ESE370 Fall2014 -- DeHon