Transcript ppt
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 27: November 5, 2014 Dynamic Logic Midterm 2 Avg: 58 Std Dev.: 15 1 Penn ESE370 Fall2014 -- DeHon Today • Clocking • Dynamic (Clocked) Logic – Strategy – Form – Compare CMOS 2 Penn ESE370 Fall2014 -- DeHon 3 Penn ESE370 Fall2014 -- DeHon Clocking 4 Penn ESE370 Fall2014 -- DeHon Two Phase Non-Overlapping Clocks • Build master-slave register from pair of latches • Control with non-overlapping clocks 5 Penn ESE370 Fall2013 -- DeHon Clocking Highlights • Clock discipline simplifies logic composition – Abstracts many internal timing details – Just concerned with making clock period long enough • Breaking logic up with registers allows to run at high frequency – reuse logic • Discipline – keeping data stable around clock edge – Setup, hold time – determined by circuit – ClkQ delay for data come out of register Penn ESE370 Fall2014 -- DeHon 6 Clocking • Circuits typically operate in a clocked environment • Gives some additional structure we can exploit 7 Penn ESE370 Fall2014 -- DeHon Dynamic Logic 8 Penn ESE370 Fall2014 -- DeHon Motivation • Like to avoid driving pullup/pulldown networks – reduce capacitive load • Power, delay 9 Penn ESE370 Fall2014 -- DeHon Motivation • Like to avoid driving pullup/pulldown networks – reduce capacitive load • Power, delay • Ratioed had problems with – Large device for ratioing – Slow pullup – Static power 10 Penn ESE370 Fall2014 -- DeHon Idea • Use clock to disable pullup during evaluation 11 Penn ESE370 Fall2014 -- DeHon Discuss • Use clock to disable pullup during evaluation • What happens when – /Pre=0, A=B=0 – /pre=1, A=B=0? – /pre=1, A=1, B=0? • Sizing implication? • Concerns? • Requirements? 12 Penn ESE370 Fall2014 -- DeHon Advantages • Large device – Driven by clock, not data/logic – Can pullup quickly w/out putting load on logic • Single network – Pulldown – Don’t have to size for ratio with pullup – Swings rail-to-rail Penn ESE370 Fall2014 -- DeHon 13 Domino Logic 14 Penn ESE370 Fall2014 -- DeHon Domino AND-OR 15 Penn ESE370 Fall2014 -- DeHon Domino • Everything charged high – After inverter all inputs low • Why do we want this? • Disabled, waiting for an enabling transition 16 Penn ESE370 Fall2014 -- DeHon Requirements • Single transition – Once fires, it is done like domino falling • All inputs at 0 during precharge – Precharge to 1 so inversion makes 0 http://en.wikipedia.org/wiki/File:Domino_effect.jpg • Non-inverting gates 17 Penn ESE370 Fall2014 -- DeHon Domino or4 18 Penn ESE370 Fall2014 -- DeHon Domino Logic • Performance – R0/2 input • Compare to CMOS cases? • nor4 • or4 • nand4 19 Penn ESE370 Fall2014 -- DeHon Dynamic OR4 • Precharge time? • Driving input – With R0/2 • Driving inverter and self cap? • Output self delay? 20 Penn ESE370 Fall2014 -- DeHon CMOS NOR4 • Driving input – With R0/2 • Driving self cap? 21 Penn ESE370 Fall2014 -- DeHon CMOS NAND4 • Driving input – w/ R0/2 • Driving self cap? 22 Penn ESE370 Fall2014 -- DeHon Issues • Noise sensitive • Power? • Activity? 23 Penn ESE370 Fall2014 -- DeHon Discuss (time permit) • Avoid inversion? • Converting from CMOS? • Post-charge 24 Penn ESE370 Fall2014 -- DeHon Observe • Better (lower) ratio of input capacitance to drive strength • Particularly good for – Driving large loads – Large fanin gates • Harder to design with – Timing and polarity restrictions – Avoiding noise • Especially with today’s high variation tech. • Can consume more energy/op Penn ESE370 Fall2014 -- DeHon 25 Idea • Dynamic/clocked logic – Only build/drive one network – Fast transition propagation – Spend delay (capacitance) on pullup off critical path of logic – More complicated, power • Reserve for when most needed 26 Penn ESE370 Fall2014 -- DeHon Admin • Homework 7 out – …and due on Tuesday • Withdraw date Friday 27 Penn ESE370 Fall2014 -- DeHon