Transcript ppt

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 10: September 19, 2014
MOS Transistor Operating Regions
Part 1
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Penn ESE370 Fall2014 -- DeHon
Today
• MOS Transistor Topology
• Threshold
• Operating Regions
– Resistive
– Saturation
– Velocity Saturation
– Subthreshold
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Last Time
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Refinement
• Depletion region  excess carriers depleted
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Body Contact
• Fourth terminal
• Also effects fields
• Usually common across transistors
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No Field
• VGS=0, VDS=0
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Apply VGS>0
• Accumulate negative charge
– Repel holes (fill holes)
++++++++
- - - - - - - - -
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Channel Evolution
Increasing Vgs
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Gate Capacitance
Changes based on operating region.
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Inversion
• Surface builds electrons
– Inverts to n-type
– Draws electrons from n+ source
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Threshold
• Voltage where strong inversion occurs
N A 
 threshold voltage
F  T ln 
– Around 2ϕF
 ni 
– Engineer by controlling doping (NA)

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Resistive Region
COX 
• VGS>VT, VDS small
OX
tOX

IDS
2 
W 
VDS
 nCOX  VGS VT VDS 

 L 
2 
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Resistive Region
COX 
• VGS>VT, VDS small
OX
tOX
• VGS fixed  looks like resistor
– Current linear in VDS

IDS
2 
W 
VDS
 nCOX  VGS VT VDS 

 L 
2 
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Linear (Resistive) Region
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Linear (Resistive) Region
Blue curve
marks transition
from Linear
to Saturation
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Dimensions
• Channel Length (L)
• Channel Width (W)
• Oxide Thickness (Tox)
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Preclass
• Ids for identical transistors in parallel?
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Preclass
• Ids for identical transistors in series?
– (Vds small)
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S
Transistor Strength (W/L)
COX 
OX
tOX
IDS
2 
W 
VDS
 nCOX  VGS VT VDS 

 L 
2 
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D
S
D
Transistor Strength (W/L)
• Shape dependence match Resistance
intuition
R
– Wider = parallel resistors  decrease R
– Longer = series resistors  increase R
IDS

L
2 
W 
VDS
 nCOX  VGS VT VDS 

 L  
2 
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A
Ldrawn vs. Leffective
• Doping not perfectly straight
• Spreads under gate
• Effective L smaller than draw gate width
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Channel Voltage
• Voltage varies along channel
• Think of channel as resistor
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Preclass 2
• What is voltage in the middle of a
resistive medium?
– (halfway between terminals)
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Voltage in Channel
• Think of channel as resistive medium
– Length = L
– Area = Width * Depth(inversion)
• What is voltage in the middle of the
channel?
– L/2 from S and D ?
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Channel Voltage
• Voltage varies along channel
• If think of channel as resistor
– Serves as a voltage divider between VS
and VD
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Impact on Inversion
• What happens when
– Vgs=2Vth ?
– Vds=2Vth?
• What is Vmiddle-Vs?
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Voltage along Channel
• What is V(x)?
x=0
x=L
V(x)
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x
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Voltage along Channel
• What is V(x)?
x=0
V(x)
Vd
Vs
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x=L
x
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Voltage along Channel
• What is V(x)?
x=0
V(x)
Vd
Vs
Penn ESE370 Fall2014 -- DeHon
x=L
x
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Voltage along Channel
• What is V(x)?
x=0
V(x)
Vd
Vs
Penn ESE370 Fall2014 -- DeHon
x=L
x
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Channel Field
• When voltage gap VG-Vxdrops below VTH,
drops out of inversion
– Occurs when: VGS-VDS< VTH
– What does this mean about conduction?
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Preclass 3
• What is Vm?
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Channel Field
• When voltage gap VG-Vxdrops below VT,
drops out of inversion
– Occurs when: VGS-VDS< VT
– What is voltage at Vmiddle if conduction stops?
– What does that mean about conduction?
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Contradiction?
• Vg-Vx < Vt  cutoff (no current)
• No current  Vg-Vx=Vgs
• Vg-Vx=Vgs > Vt  current flows
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Way out?
• Vg-Vx < Vt  cutoff (no current)
• No current  Vg-Vx=Vgs
• Vg-Vx=Vgs > Vt  current flows
Act like
Vds at
Vgs-Vt
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Channel Field
• When voltage gap VG-Vxdrops below VT,
drops out of inversion
– Occurs when: VGS-VDS< VT
– Channel is “pinched off”
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Channel Field
• When voltage gap VG-Vxdrops below VT,
drops out of inversion
– Occurs when: VGS-VDS< VT
– Channel is “pinched off”
– Current will flow, but cannot increase any
further
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Pinch Off
• When voltage drops below VT, drops
out of inversion
– Occurs when: VGS-VDS< VT
• Conclusion:
– current cannot increase with VDS once
VDS> VGS-VT
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
Saturation
• In saturation, VDS-effective=Vx= VGS-VT
IDS
2 
W 
VDS
 nCOX  VGS VT VDS 

 L 
2 
• Becomes:
IDS
2 

VGS  VT 
W 
2


 n COX  VGS  VT  
 L 
2



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Saturation
• VDS> VGS-VT
IDS
2 

VGS  VT 
W 
2


 n COX  VGS  VT  
 L 
2



IDS 

n COX W 
2
  VGS  VT 
 L 
2

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Saturation Region
Blue curve
marks transition
from Linear
to Saturation
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Switching Operation
•
•
•
•
Consider Inverter
Start with in=0V
Output voltage?
What does first-order
model say about NFET?
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Switching Operation
•
•
•
•
•
Input rises from 0V
When cross into new region?
What region cross into?
Ids Current?
What happens to Ids as
V continues to rise?
• What is happening to Vout?
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Switching Operation
• Input reches Vdd
• When does NFET change
operating regions?
• Which region move into?
• What’s happening to Vout?
• What region when settles
to static voltage?
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Retrace Transition
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Approach
• Identify Region
• Drives governing equations
• Use to understand operation
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Big Idea
• 3 Regions of
operation for
MOSFET
– Subthreshold
– Resistive
– Saturation
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Admin
• Text 3.3.2 – highly recommend read
– Second half on Friday
• HW4 out
– Get started over weekend
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