Transcript ppt
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 31: November 23, 2011 Crosstalk 1 Penn ESE370 Fall2011 -- DeHon Today • Crosstalk – How arise – Consequences – Magnitude – Avoiding 2 Penn ESE370 Fall2011 -- DeHon Capacitance • There are capacitors everywhere • Already talked about – Wires as capacitors – Capacitance between terminals on transistor 3 Penn ESE370 Fall2011 -- DeHon Miller Effect • For an inverting gate • Capacitance between input and output must swing 2 Vhigh • Or…acts as doublesized capacitor 4 Penn ESE370 Fall2011 -- DeHon Capacitance Everywhere • Potentially a capacitor between any two conductors – On the chip – On the package – On the board • All wires – – – – Package pins PCB traces Cable wires Bit lines 5 Penn ESE370 Fall2011 -- DeHon Capacitor Dependence • Decrease with conductor separation • Increase with size • Depends on dielectric A C r 0 d Penn ESE370 Fall2011 -- DeHon 6 Parallel Wires • Parallel-plate capacitance between wires 7 Penn ESE370 Fall2011 -- DeHon Wire Capacitance • Changes in voltage on one wire may couple through capacitance to another 8 Penn ESE370 Fall2011 -- DeHon Consequences Qualitative First 9 Penn ESE370 Fall2011 -- DeHon Driven Wire • What happens to a driven wire? 10 Penn ESE370 Fall2011 -- DeHon Driven Wire • Can this be a problem? • Victim – Clock line – Asynchronous control – Non-clock used in synchronous system • Outputs sampled at clock edge 11 Penn ESE370 Fall2011 -- DeHon Undriven Wire • What happens to undriven wire? • Where do we have undriven wires? 12 Penn ESE370 Fall2011 -- DeHon Clocked Logic • CMOS driven lines • Clocked logic • Willing to wait to settle • Impact is solely on delay – May increase delay of transitions 13 Penn ESE370 Fall2011 -- DeHon Magnitude Quantitative 14 Penn ESE370 Fall2011 -- DeHon How large is the noise? • V1 transitions from 0 to V? 15 Penn ESE370 Fall2011 -- DeHon How large is the noise? • V1 transitions from 0 to V I CdV /dt C1(d(V1 V2 )/dt) C2 (dV2 /dt) C1(dV1 /dt) C1 C2 (dV2 /dt) Penn ESE370 Fall2011 -- DeHon 16 Noise Magnitude C1(dV1 /dt) C1 C2 (dV2 /dt) C1V1 C1 C2 V2 C1 V2 V1 C1 C2 Penn ESE370 Fall2011 -- DeHon 17 SPICE C1=10pF, C2=20pF 18 Penn ESE370 Fall2011 -- DeHon Good (?) Capacitance • High capacitance to ground plane – Limits node swing from adjacent conductors C1 V2 V1 C1 C2 Penn ESE370 Fall2011 -- DeHon 19 Driven Line • What happens when victim line is driven? 20 Penn ESE370 Fall2011 -- DeHon Driven Line • Driven line – Recovers with time constant: R2(C1+C2) 21 Penn ESE370 Fall2011 -- DeHon Spice: R2=1K, C1=10pF, C2=20pF 22 Penn ESE370 Fall2011 -- DeHon Magnitude of Noise on Driven Line • Magnitude of diversion depends on relative time constants t1, t2 t1<< t2 • full diversion, then recover t1>> t2 • Charge capacitor faster than line 1 can change – little noise 23 Penn ESE370 Fall2011 -- DeHon Magnitude of Noise on Driven Line • Magnitude of diversion depends on relative time constants t1, t2 t1<< t2 t1>> t2 24 Penn ESE370 Fall2011 -- DeHon Spice: C1=1pF, C2=2pF 25 Penn ESE370 Fall2011 -- DeHon Simultaneous Transition • What happens if transition in opposite directions? 26 Penn ESE370 Fall2011 -- DeHon Simultaneous Transition • What happens if transition in opposite directions? – Must charge C1 by 2V – Or looks like 2C1 between wires 27 Penn ESE370 Fall2011 -- DeHon Where Arise 28 Penn ESE370 Fall2011 -- DeHon Cables and PCB Wires Source; http://en.wikipedia.org/wiki/File:Flachbandkabel.jpg 29 Penn ESE370 Fall2011 -- DeHon Printed Circuit Board Source: http://en.wikipedia.org/wiki/File:Testpad.JPG Penn ESE370 Fall2011 -- DeHon 30 Interconnect Cross Section Penn ESE370 Fall2011 -- DeHon ITRS 2007 31 IC Metalization Source: http://en.wikipedia.org/wiki/File:Silicon_chip_3d.png Penn ESE370 Fall2011 -- DeHon 32 Standard Cell Area All cells uniform height inv nand3 Width of channel determined by routing Cell area Identify the full custom and standard cell regions on 386DX die http://microscope.fsu.edu/chipshots/intel/386dxlarge.html 33 Penn ESE370 Fall2011 -- DeHon Wires • Will be capacitively coupled to many adjacent wires of varying degrees 34 Penn ESE370 Fall2011 -- DeHon bit lines, word lines wordline bitline 35 Penn ESE370 Fall2011 -- DeHon Source: http://techon.nikkeibp.co.jp/article/HONSHI/20071219/144399/ Addressing 36 Penn ESE370 Fall2011 -- DeHon What can we do? • How can we reduce? 37 Penn ESE370 Fall2011 -- DeHon What can we do? • Orthogonal routing layers – Avoid parallel coupling vertically • Widen spacing between wires – Particularly critical path wires • Limit length two wires run in parallel • Separate with power planes • Separate with ground/power wires 38 Penn ESE370 Fall2011 -- DeHon Admin • HW6 Out by time return from break • Next week – Project 3 out – Lecture Monday and Wednesday – Lab on Friday 39 Penn ESE370 Fall2011 -- DeHon Idea • • • • Capacitance is everywhere Especially between adjacent wires Will get “noise” from crosstalk Clocked and driven wires – Slow down transitions • Undriven wires voltage changed • Can cause spurious transitions 40 Penn ESE370 Fall2011 -- DeHon